[llvm] Enable Custom Lowering for fabs.v8f16 on AVX (PR #71730)
David Li via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 16 12:59:14 PST 2023
https://github.com/david-xl updated https://github.com/llvm/llvm-project/pull/71730
>From 8fc364a1cf2de8c6968ec8a0adca6ff45239806d Mon Sep 17 00:00:00 2001
From: David Li <davidxl at google.com>
Date: Tue, 7 Nov 2023 23:29:44 -0800
Subject: [PATCH 1/6] Enable Custom Lowering for fabs.v8f16 on AVX
modified: llvm/lib/Target/X86/X86ISelLowering.cpp
modified: llvm/test/CodeGen/X86/vec_fabs.ll
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 3 ++
llvm/test/CodeGen/X86/vec_fabs.ll | 39 +++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c9381218eee7840..1b263fcf9133f1a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2242,6 +2242,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}
}
+ if (Subtarget.hasAVX())
+ setOperationAction(ISD::FABS, MVT::v8f16, Custom);
+
if (!Subtarget.useSoftFloat() &&
(Subtarget.hasAVXNECONVERT() || Subtarget.hasBF16())) {
addRegisterClass(MVT::v8bf16, Subtarget.hasAVX512() ? &X86::VR128XRegClass
diff --git a/llvm/test/CodeGen/X86/vec_fabs.ll b/llvm/test/CodeGen/X86/vec_fabs.ll
index 8876d2f9b19928e..8a34c54b752e06c 100644
--- a/llvm/test/CodeGen/X86/vec_fabs.ll
+++ b/llvm/test/CodeGen/X86/vec_fabs.ll
@@ -137,6 +137,45 @@ define <4 x double> @fabs_v4f64(<4 x double> %p) {
}
declare <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
+define <8 x half> @fabs_v8f16(ptr %p) {
+; X86-AVX-LABEL: fabs_v8f16:
+; X86-AVX: # %bb.0:
+; X86-AVX-NEXT: movl 4(%esp), [[ADDRREG:%.*]]
+; X86-AVX-NEXT: vmovaps ([[ADDRREG]]), %xmm0
+; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: retl
+
+; X86-AVX2-LABEL: fabs_v8f16:
+; X86-AVX2: # %bb.0:
+; X86-AVX2-NEXT: movl 4(%esp), [[REG:%.*]]
+; X86-AVX2-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-AVX2-NEXT: vpand ([[REG]]), %xmm0, %xmm0
+; X86-AVX2-NEXT: retl
+
+; X64-AVX512VL-LABEL: fabs_v8f16:
+; X64-AVX512VL: # %bb.0:
+; X64-AVX512VL-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-AVX512VL-NEXT: vpand (%rdi), %xmm0, %xmm0
+; X64-AVX512VL-NEXT: retq
+
+; X64-AVX-LABEL: fabs_v8f16:
+; X64-AVX: # %bb.0:
+; X64-AVX-NEXT: vmovaps (%rdi), %xmm0
+; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: retq
+
+; X64-AVX2-LABEL: fabs_v8f16:
+; X64-AVX2: # %bb.0:
+; X64-AVX2-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-AVX2-NEXT: vpand (%rdi), %xmm0, %xmm0
+; X64-AVX2-NEXT: retq
+
+ %v = load <8 x half>, ptr %p, align 16
+ %nnv = call <8 x half> @llvm.fabs.v8f16(<8 x half> %v)
+ ret <8 x half> %nnv
+}
+declare <8 x half> @llvm.fabs.v8f16(<8 x half> %p)
+
define <8 x float> @fabs_v8f32(<8 x float> %p) {
; X86-AVX1-LABEL: fabs_v8f32:
; X86-AVX1: # %bb.0:
>From adfb5b4e8ae810a4306ef1164ebe0982c58c62d2 Mon Sep 17 00:00:00 2001
From: David Li <davidxl at google.com>
Date: Wed, 8 Nov 2023 11:05:15 -0800
Subject: [PATCH 2/6] Check softfloat setting for fabs.v8f16 custom lowering
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1b263fcf9133f1a..17841c8bda7ba5d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2242,7 +2242,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}
}
- if (Subtarget.hasAVX())
+ if (!Subtarget.useSoftFloat() && Subtarget.hasAVX())
setOperationAction(ISD::FABS, MVT::v8f16, Custom);
if (!Subtarget.useSoftFloat() &&
>From 7898ac76c701bb412a521fcd30bcaa6aa0b62435 Mon Sep 17 00:00:00 2001
From: David Li <davidxl at google.com>
Date: Tue, 7 Nov 2023 23:29:44 -0800
Subject: [PATCH 3/6] Enable Custom Lowering for fabs.v8f16 on AVX
---
llvm/test/CodeGen/X86/vec_fabs.ll | 42 +++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/llvm/test/CodeGen/X86/vec_fabs.ll b/llvm/test/CodeGen/X86/vec_fabs.ll
index 8a34c54b752e06c..b933bb6ae2530df 100644
--- a/llvm/test/CodeGen/X86/vec_fabs.ll
+++ b/llvm/test/CodeGen/X86/vec_fabs.ll
@@ -139,6 +139,48 @@ declare <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
define <8 x half> @fabs_v8f16(ptr %p) {
; X86-AVX-LABEL: fabs_v8f16:
+<<<<<<< HEAD
+=======
+; X86-AVX: # %bb.0:
+; X86-AVX-NEXT: movl 4(%esp), [[ADDRREG:%.*]]
+; X86-AVX-NEXT: vmovaps ([[ADDRREG]]), %xmm0
+; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT: retl
+
+; X86-AVX2-LABEL: fabs_v8f16:
+; X86-AVX2: # %bb.0:
+; X86-AVX2-NEXT: movl 4(%esp), [[REG:%.*]]
+; X86-AVX2-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-AVX2-NEXT: vpand ([[REG]]), %xmm0, %xmm0
+; X86-AVX2-NEXT: retl
+
+; X64-AVX512VL-LABEL: fabs_v8f16:
+; X64-AVX512VL: # %bb.0:
+; X64-AVX512VL-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-AVX512VL-NEXT: vpand (%rdi), %xmm0, %xmm0
+; X64-AVX512VL-NEXT: retq
+
+; X64-AVX-LABEL: fabs_v8f16:
+; X64-AVX: # %bb.0:
+; X64-AVX-NEXT: vmovaps (%rdi), %xmm0
+; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT: retq
+
+; X64-AVX2-LABEL: fabs_v8f16:
+; X64-AVX2: # %bb.0:
+; X64-AVX2-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-AVX2-NEXT: vpand (%rdi), %xmm0, %xmm0
+; X64-AVX2-NEXT: retq
+
+ %v = load <8 x half>, ptr %p, align 16
+ %nnv = call <8 x half> @llvm.fabs.v8f16(<8 x half> %v)
+ ret <8 x half> %nnv
+}
+declare <8 x half> @llvm.fabs.v8f16(<8 x half> %p)
+
+define <8 x float> @fabs_v8f32(<8 x float> %p) {
+; X86-AVX-LABEL: fabs_v8f32:
+>>>>>>> 6032b965f854 (Enable Custom Lowering for fabs.v8f16 on AVX)
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: movl 4(%esp), [[ADDRREG:%.*]]
; X86-AVX-NEXT: vmovaps ([[ADDRREG]]), %xmm0
>From c5c66704bae6185e73d045b1985de7bbc7a306a8 Mon Sep 17 00:00:00 2001
From: David Li <davidxl at google.com>
Date: Tue, 7 Nov 2023 23:29:44 -0800
Subject: [PATCH 4/6] Enable Custom Lowering for fabs.v8f16 on AVX
modified: llvm/test/CodeGen/X86/vec_fabs.ll
---
llvm/test/CodeGen/X86/vec_fabs.ll | 3 +++
1 file changed, 3 insertions(+)
diff --git a/llvm/test/CodeGen/X86/vec_fabs.ll b/llvm/test/CodeGen/X86/vec_fabs.ll
index b933bb6ae2530df..e30ae697f464ca7 100644
--- a/llvm/test/CodeGen/X86/vec_fabs.ll
+++ b/llvm/test/CodeGen/X86/vec_fabs.ll
@@ -140,7 +140,10 @@ declare <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
define <8 x half> @fabs_v8f16(ptr %p) {
; X86-AVX-LABEL: fabs_v8f16:
<<<<<<< HEAD
+<<<<<<< HEAD
+=======
=======
+>>>>>>> f2f313666780 (Enable Custom Lowering for fabs.v8f16 on AVX)
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: movl 4(%esp), [[ADDRREG:%.*]]
; X86-AVX-NEXT: vmovaps ([[ADDRREG]]), %xmm0
>From 205507fe6d7a9e3ee6800ccf8e6a68a70eefc5be Mon Sep 17 00:00:00 2001
From: David Li <davidxl at google.com>
Date: Tue, 7 Nov 2023 23:29:44 -0800
Subject: [PATCH 5/6] Enable Custom Lowering for fabs.v8f16 on AVX
modified: llvm/test/CodeGen/X86/vec_fabs.ll
modified: llvm/test/CodeGen/X86/vec_fabs.ll
modified: llvm/test/CodeGen/X86/vec_fabs.ll
---
llvm/test/CodeGen/X86/vec_fabs.ll | 67 +++++--------------------------
1 file changed, 11 insertions(+), 56 deletions(-)
diff --git a/llvm/test/CodeGen/X86/vec_fabs.ll b/llvm/test/CodeGen/X86/vec_fabs.ll
index e30ae697f464ca7..23ca7a91764ce3c 100644
--- a/llvm/test/CodeGen/X86/vec_fabs.ll
+++ b/llvm/test/CodeGen/X86/vec_fabs.ll
@@ -138,57 +138,12 @@ define <4 x double> @fabs_v4f64(<4 x double> %p) {
declare <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
define <8 x half> @fabs_v8f16(ptr %p) {
-; X86-AVX-LABEL: fabs_v8f16:
-<<<<<<< HEAD
-<<<<<<< HEAD
-=======
-=======
->>>>>>> f2f313666780 (Enable Custom Lowering for fabs.v8f16 on AVX)
-; X86-AVX: # %bb.0:
-; X86-AVX-NEXT: movl 4(%esp), [[ADDRREG:%.*]]
-; X86-AVX-NEXT: vmovaps ([[ADDRREG]]), %xmm0
-; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X86-AVX-NEXT: retl
-
-; X86-AVX2-LABEL: fabs_v8f16:
-; X86-AVX2: # %bb.0:
-; X86-AVX2-NEXT: movl 4(%esp), [[REG:%.*]]
-; X86-AVX2-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-AVX2-NEXT: vpand ([[REG]]), %xmm0, %xmm0
-; X86-AVX2-NEXT: retl
-
-; X64-AVX512VL-LABEL: fabs_v8f16:
-; X64-AVX512VL: # %bb.0:
-; X64-AVX512VL-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-AVX512VL-NEXT: vpand (%rdi), %xmm0, %xmm0
-; X64-AVX512VL-NEXT: retq
-
-; X64-AVX-LABEL: fabs_v8f16:
-; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vmovaps (%rdi), %xmm0
-; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; X64-AVX-NEXT: retq
-
-; X64-AVX2-LABEL: fabs_v8f16:
-; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-AVX2-NEXT: vpand (%rdi), %xmm0, %xmm0
-; X64-AVX2-NEXT: retq
-
- %v = load <8 x half>, ptr %p, align 16
- %nnv = call <8 x half> @llvm.fabs.v8f16(<8 x half> %v)
- ret <8 x half> %nnv
-}
-declare <8 x half> @llvm.fabs.v8f16(<8 x half> %p)
-
-define <8 x float> @fabs_v8f32(<8 x float> %p) {
-; X86-AVX-LABEL: fabs_v8f32:
->>>>>>> 6032b965f854 (Enable Custom Lowering for fabs.v8f16 on AVX)
-; X86-AVX: # %bb.0:
-; X86-AVX-NEXT: movl 4(%esp), [[ADDRREG:%.*]]
-; X86-AVX-NEXT: vmovaps ([[ADDRREG]]), %xmm0
-; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X86-AVX-NEXT: retl
+; X86-AVX1-LABEL: fabs_v8f16:
+; X86-AVX1: # %bb.0:
+; X86-AVX1-NEXT: movl 4(%esp), [[ADDRREG:%.*]]
+; X86-AVX1-NEXT: vmovaps ([[ADDRREG]]), %xmm0
+; X86-AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX1-NEXT: retl
; X86-AVX2-LABEL: fabs_v8f16:
; X86-AVX2: # %bb.0:
@@ -203,11 +158,11 @@ define <8 x float> @fabs_v8f32(<8 x float> %p) {
; X64-AVX512VL-NEXT: vpand (%rdi), %xmm0, %xmm0
; X64-AVX512VL-NEXT: retq
-; X64-AVX-LABEL: fabs_v8f16:
-; X64-AVX: # %bb.0:
-; X64-AVX-NEXT: vmovaps (%rdi), %xmm0
-; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; X64-AVX-NEXT: retq
+; X64-AVX1-LABEL: fabs_v8f16:
+; X64-AVX1: # %bb.0:
+; X64-AVX1-NEXT: vmovaps (%rdi), %xmm0
+; X64-AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-AVX1-NEXT: retq
; X64-AVX2-LABEL: fabs_v8f16:
; X64-AVX2: # %bb.0:
>From 3ae532b668d5992324ec422aa561748a6fe29070 Mon Sep 17 00:00:00 2001
From: David Li <davidxl at google.com>
Date: Wed, 15 Nov 2023 11:59:14 -0800
Subject: [PATCH 6/6] Address review comments
1. Move the code to the common place
2. Add test coverage for v16f16 and v32f16 FABS lowering
modified: llvm/lib/Target/X86/X86ISelLowering.cpp
modified: llvm/test/CodeGen/X86/vec_fabs.ll
modified: llvm/lib/Target/X86/X86ISelLowering.cpp
modified: llvm/test/CodeGen/X86/vec_fabs.ll
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 5 ++-
llvm/test/CodeGen/X86/vec_fabs.ll | 43 +++++++++++++++++++++++++
2 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 17841c8bda7ba5d..7f9d971ceeeeaf6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1396,6 +1396,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FMINIMUM, VT, Custom);
}
+ setOperationAction(ISD::FABS, MVT::v8f16, Custom);
+
// (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
// even though v8i16 is a legal type.
setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32);
@@ -2242,9 +2244,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}
}
- if (!Subtarget.useSoftFloat() && Subtarget.hasAVX())
- setOperationAction(ISD::FABS, MVT::v8f16, Custom);
-
if (!Subtarget.useSoftFloat() &&
(Subtarget.hasAVXNECONVERT() || Subtarget.hasBF16())) {
addRegisterClass(MVT::v8bf16, Subtarget.hasAVX512() ? &X86::VR128XRegClass
diff --git a/llvm/test/CodeGen/X86/vec_fabs.ll b/llvm/test/CodeGen/X86/vec_fabs.ll
index 23ca7a91764ce3c..8af067d88a57e96 100644
--- a/llvm/test/CodeGen/X86/vec_fabs.ll
+++ b/llvm/test/CodeGen/X86/vec_fabs.ll
@@ -2,10 +2,12 @@
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=X86,X86-AVX,X86-AVX1
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=X86,X86-AVX,X86-AVX2
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefixes=X86,X86-AVX512VL
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512fp16 | FileCheck %s --check-prefixes=X86,X86-AVX512FP16
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefixes=X86,X86-AVX512VLDQ
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefixes=X64,X64-AVX512VL
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16 | FileCheck %s --check-prefixes=X64,X64-AVX512FP16
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefixes=X64,X64-AVX512VLDQ
define <2 x double> @fabs_v2f64(<2 x double> %p) {
@@ -176,6 +178,47 @@ define <8 x half> @fabs_v8f16(ptr %p) {
}
declare <8 x half> @llvm.fabs.v8f16(<8 x half> %p)
+define <16 x half> @fabs_v16f16(ptr %p) {
+; X86-AVX512FP16-LABEL: fabs_v16f16:
+; X86-AVX512FP16: # %bb.0:
+; X86-AVX512FP16-NEXT: movl 4(%esp), [[REG:%.*]]
+; X86-AVX512FP16-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}, [[YMM:%ymm[0-9]+]]
+; X86-AVX512FP16-NEXT: vpand ([[REG]]), [[YMM]], [[YMM]]
+; X86-AVX512FP16-NEXT: retl
+
+; X64-AVX512FP16-LABEL: fabs_v16f16:
+; X64-AVX512FP16: # %bb.0:
+; X64-AVX512FP16-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), [[YMM:%ymm[0-9]+]]
+; X64-AVX512FP16-NEXT: vpand (%rdi), [[YMM]], [[YMM]]
+; X64-AVX512FP16-NEXT: retq
+;
+ %v = load <16 x half>, ptr %p, align 32
+ %nnv = call <16 x half> @llvm.fabs.v16f16(<16 x half> %v)
+ ret <16 x half> %nnv
+}
+declare <16 x half> @llvm.fabs.v16f16(<16 x half> %p)
+
+define <32 x half> @fabs_v32f16(ptr %p) {
+; X86-AVX512FP16-LABEL: fabs_v32f16:
+; X86-AVX512FP16: # %bb.0:
+; X86-AVX512FP16-NEXT: movl 4(%esp), [[REG:%.*]]
+; X86-AVX512FP16-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}, [[ZMM:%zmm[0-9]+]]
+; X86-AVX512FP16-NEXT: vpandq ([[REG]]), [[ZMM]], [[ZMM]]
+; X86-AVX512FP16-NEXT: retl
+
+; X64-AVX512FP16-LABEL: fabs_v32f16:
+; X64-AVX512FP16: # %bb.0:
+; X64-AVX512FP16-NEXT: vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), [[ZMM:%zmm[0-9]+]]
+; X64-AVX512FP16-NEXT: vpandq (%rdi), [[ZMM]], [[ZMM]]
+; X64-AVX512FP16-NEXT: retq
+
+ %v = load <32 x half>, ptr %p, align 64
+ %nnv = call <32 x half> @llvm.fabs.v32f16(<32 x half> %v)
+ ret <32 x half> %nnv
+}
+declare <32 x half> @llvm.fabs.v32f16(<32 x half> %p)
+
+
define <8 x float> @fabs_v8f32(<8 x float> %p) {
; X86-AVX1-LABEL: fabs_v8f32:
; X86-AVX1: # %bb.0:
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