[llvm] [RISCV] Reorder the vector register allocation sequence. (PR #69290)

[Philip Reames via llvm-commits]

preames wrote:

I think we're probably going to need to have the allocation order depend on the calling convention.  For the proposed vector calling convention, having our allocation order prefer callee saved registers is the last thing we want.  For the default scalar convention (which has no vector callee saves), preferring the fragmented registers in the first LMUL8 group (i.e. this change) is probably reasonable.

Do you have any performance data with this change?  On the surface, this seems reasonable, but I'm curious about empirical evaluation.

p.s. There are some unrelated style changes rolled into the change which can probably be separated.  Specifically, definition order and use of sequence vs hard coded lists.  

https://github.com/llvm/llvm-project/pull/69290