[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)

Michael Maitland via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 16 07:57:26 PST 2023

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michaelmaitland wrote:

This PR has been committed in f219e03f3c9bea4220925838c3d57d5a993d4d7a and dbd884cd3da720b0adbd52142f1426745ab9d181.

https://github.com/llvm/llvm-project/pull/71541

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