[llvm] [AMDGPU] Reimplement PreRARematStage stage for the GCNSchedStrategy. Early-preview, WIP. (PR #72505)

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git-clang-format --diff 865f54e501739f382d33866baebfd0f9aaad01bb 3e6e768a05d51f283799db78d6a9c3c8374d1e62 -- llvm/lib/Target/AMDGPU/GCNSinkTRInstr.cpp llvm/lib/Target/AMDGPU/GCNSinkTRInstr.h llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp llvm/lib/Target/AMDGPU/GCNRegPressure.cpp llvm/lib/Target/AMDGPU/GCNRegPressure.h llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp llvm/lib/Target/AMDGPU/GCNSchedStrategy.h llvm/lib/Target/AMDGPU/GCNSubtarget.h
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diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
index 20a5183c1c..f1eb04a324 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -64,11 +64,10 @@ GCNRegPressure::getRegExcessMask(Register Reg, const MachineRegisterInfo &MRI) {
   assert(Reg.isVirtual());
   const auto RC = MRI.getRegClass(Reg);
   auto STI = static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
-  return STI->isSGPRClass(RC)
-             ? (1ul << SGPR32)
-             : STI->isVGPRClass(RC)
-                   ? (1ul << VGPR32)
-                   : STI->isAGPRClass(RC) ? (1ul << AGPR32) : 0;
+  return STI->isSGPRClass(RC)   ? (1ul << SGPR32)
+         : STI->isVGPRClass(RC) ? (1ul << VGPR32)
+         : STI->isAGPRClass(RC) ? (1ul << AGPR32)
+                                : 0;
 }
 
 GCNRegPressure GCNRegPressure::getMaxPressure(unsigned Occupancy,

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https://github.com/llvm/llvm-project/pull/72505