[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 15 20:16:01 PST 2023
================
@@ -12764,6 +12788,15 @@ struct NodeExtensionHelper {
/// Check if \p Root supports any extension folding combines.
static bool isSupportedRoot(const SDNode *Root) {
switch (Root->getOpcode()) {
+ case ISD::ADD:
+ case ISD::SUB:
+ case ISD::MUL: {
+ EVT VT0 = Root->getOperand(0).getValueType();
----------------
sun-jacobi wrote:
You are right, It will be safer to do this, I will fix it soon.
https://github.com/llvm/llvm-project/pull/72340
More information about the llvm-commits
mailing list