[llvm] [AMDGPU] Allocate i1 argument to SGPRs (PR #72461)

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``````````bash
git-clang-format --diff 212a60ec37322f853e91e171b305479b1abff2f2 e8f4ad2c2b01794cd3283edf846efb84b5efccaf -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 800f6cb84a..6f74b8ac99 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3474,11 +3474,14 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
   // reserve these registers.
   if (!Subtarget->enableFlatScratch()) {
     if (IsChainCallConv)
-      CCInfo.AllocateRegBlock(ArrayRef<MCPhysReg>{
-          AMDGPU::SGPR48, AMDGPU::SGPR49, AMDGPU::SGPR50, AMDGPU::SGPR51}, 4);
+      CCInfo.AllocateRegBlock(
+          ArrayRef<MCPhysReg>{AMDGPU::SGPR48, AMDGPU::SGPR49, AMDGPU::SGPR50,
+                              AMDGPU::SGPR51},
+          4);
     else
-      CCInfo.AllocateRegBlock(ArrayRef<MCPhysReg>{
-          AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3}, 4);
+      CCInfo.AllocateRegBlock(ArrayRef<MCPhysReg>{AMDGPU::SGPR0, AMDGPU::SGPR1,
+                                                  AMDGPU::SGPR2, AMDGPU::SGPR3},
+                              4);
   }
 
   CCInfo.AnalyzeCallOperands(Outs, AssignFn);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index ac12210766..1432feec9e 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -898,13 +898,14 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       // When an i1 argument is allocated to an SGPR_32, we may have a COPY
       // from SGPR_32 to SReg_64. The following handles this case to avoid
       // an illegal copy.
-      if(AMDGPU::SGPR_32RegClass.contains(SrcReg)) {
+      if (AMDGPU::SGPR_32RegClass.contains(SrcReg)) {
         auto sub0 = RI.getSubReg(DestReg, AMDGPU::sub0);
         if (sub0 != SrcReg) {
           BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), sub0).addReg(SrcReg);
         }
         BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32),
-                RI.getSubReg(DestReg, AMDGPU::sub1)).addImm(0);
+                RI.getSubReg(DestReg, AMDGPU::sub1))
+            .addImm(0);
         return;
       }
 
diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
index 0817a2b164..999bc09989 100644
--- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -506,7 +506,7 @@ bool SILowerI1Copies::lowerCopiesFromI1() {
       // When the calling convention allocates i1 argument to SGPR,
       // we may have a COPY with dst being an SGPR_32. This should
       // not be lowered into V_CNDMASK_B32.
-      if(AMDGPU::SGPR_32RegClass.contains(DstReg))
+      if (AMDGPU::SGPR_32RegClass.contains(DstReg))
         continue;
 
       Changed = true;
@@ -617,8 +617,7 @@ bool SILowerI1Copies::lowerPhis() {
 
       for (unsigned i = 0; i < IncomingRegs.size(); ++i) {
         IncomingUpdated.push_back(createLaneMaskReg(*MF));
-        SSAUpdater.AddAvailableValue(IncomingBlocks[i],
-                                     IncomingUpdated.back());
+        SSAUpdater.AddAvailableValue(IncomingBlocks[i], IncomingUpdated.back());
       }
 
       for (unsigned i = 0; i < IncomingRegs.size(); ++i) {

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https://github.com/llvm/llvm-project/pull/72461