[llvm] [AMDGPU] RA inserted scalar instructions can be at the BB top (PR #72140)

[Stanislav Mekhanoshin via llvm-commits]

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@@ -846,8 +846,10 @@ class MachineBasicBlock
 
   /// Return the first instruction in MBB after I that is not a PHI, label or
   /// debug.  This is the correct point to insert copies at the beginning of a
-  /// basic block.
-  iterator SkipPHIsLabelsAndDebug(iterator I, bool SkipPseudoOp = true);
+  /// basic block. \p Reg is the register being defined for a spill/split during
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rampitec wrote:

Actually spill does not define a register, it kills it. Restore defines register.

https://github.com/llvm/llvm-project/pull/72140