[llvm] 084f5c2 - [RISCV] Add tests cases to show missed opportunity to turn vfmv.s.f into vmv.s.x when source is FP constant materialized in GPR.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-15T10:51:43-08:00
New Revision: 084f5c26a4ad174bfbe1f6ba28385c6324c13bd1

URL: https://github.com/llvm/llvm-project/commit/084f5c26a4ad174bfbe1f6ba28385c6324c13bd1
DIFF: https://github.com/llvm/llvm-project/commit/084f5c26a4ad174bfbe1f6ba28385c6324c13bd1.diff

LOG: [RISCV] Add tests cases to show missed opportunity to turn vfmv.s.f into vmv.s.x when source is FP constant materialized in GPR.

We end up creating the constant in GPR, move to FPR, then move to vector.
We should go directly from GPR to vector.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
index fa80f9824d85d00..1cc5f7906ede84c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \
-; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \
-; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
+; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV64
 
 declare <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half>, half, iXLen)
 
@@ -363,3 +363,50 @@ entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double> %0, double 0.0, iXLen %1)
   ret <vscale x 8 x double> %a
 }
+
+define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_nxv1f16_negzero(<vscale x 1 x half> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f16_negzero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a1, 1048568
+; CHECK-NEXT:    fmv.h.x fa5, a1
+; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT:    vfmv.s.f v8, fa5
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half> %0, half -0.0, iXLen %1)
+  ret <vscale x 1 x half> %a
+}
+
+define <vscale x 1 x float> @intrinsic_vfmv.s.f_f_nxv1f32_negzero(<vscale x 1 x float> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f32_negzero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a1, 524288
+; CHECK-NEXT:    fmv.w.x fa5, a1
+; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT:    vfmv.s.f v8, fa5
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float> %0, float -0.0, iXLen %1)
+  ret <vscale x 1 x float> %a
+}
+
+define <vscale x 1 x double> @intrinsic_vfmv.s.f_f_nxv1f64_negzero(<vscale x 1 x double> %0, iXLen %1) nounwind {
+; RV32-LABEL: intrinsic_vfmv.s.f_f_nxv1f64_negzero:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    fcvt.d.w fa5, zero
+; RV32-NEXT:    fneg.d fa5, fa5
+; RV32-NEXT:    vsetvli zero, a0, e64, m1, tu, ma
+; RV32-NEXT:    vfmv.s.f v8, fa5
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: intrinsic_vfmv.s.f_f_nxv1f64_negzero:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    fmv.d.x fa5, zero
+; RV64-NEXT:    fneg.d fa5, fa5
+; RV64-NEXT:    vsetvli zero, a0, e64, m1, tu, ma
+; RV64-NEXT:    vfmv.s.f v8, fa5
+; RV64-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double> %0, double -0.0, iXLen %1)
+  ret <vscale x 1 x double> %a
+}