[llvm] 05f70f7 - [RISCV] Add IsSignExtendingOpW to LR_W and SC_W as well. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 15 09:56:42 PST 2023
Author: Craig Topper
Date: 2023-11-15T09:56:36-08:00
New Revision: 05f70f7987f6bb34393b6ea0781c1060234a22ea
URL: https://github.com/llvm/llvm-project/commit/05f70f7987f6bb34393b6ea0781c1060234a22ea
DIFF: https://github.com/llvm/llvm-project/commit/05f70f7987f6bb34393b6ea0781c1060234a22ea.diff
LOG: [RISCV] Add IsSignExtendingOpW to LR_W and SC_W as well. NFC
These instructions don't exist in the CodeGen pipeline early
enough for RISCVOptWInstrs to see them, but they still have the property.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoA.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index c9ff9b4872d4aba..c8301fcc6b93886 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -48,12 +48,10 @@ multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
// Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [HasStdExtA] in {
+let Predicates = [HasStdExtA], IsSignExtendingOpW = 1 in {
defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">,
Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>;
-
-let IsSignExtendingOpW = 1 in {
defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">,
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">,
@@ -72,7 +70,6 @@ defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">,
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">,
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
-}
} // Predicates = [HasStdExtA]
let Predicates = [HasStdExtA, IsRV64] in {
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