[llvm] [RISCV] Add macro fusions for Xiangshan (PR #72362)

Yingwei Zheng via llvm-commits llvm-commits at lists.llvm.org
Wed Nov 15 08:01:06 PST 2023


================
@@ -0,0 +1,114 @@
+//==----- RISCVMacroFusion.td - Macro Fusion Definitions -----*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// ===---------------------------------------------------------------------===//
+// The following definitions describe the macro fusion predicators.
+
+class RISCVMacroFusionCommon<list<Instruction> first,list<Instruction> second,
+                             list<MCInstPredicate> extraFirstPreds = [],
+                             list<MCInstPredicate> extraSecondPreds = [],
+                             list<MacroFusionPredicateBase> extraProlog = [],
+                             list<MacroFusionPredicateBase> extraEpilog = []>
+  : MacroFusion<CheckAll<!listconcat([CheckOpcode<first>], extraFirstPreds)>,
+                CheckAll<!listconcat([
+                  CheckOpcode<second>,
+                  CheckAny<[
+                    CheckIsVRegOperand<0>,
+                    CheckSameRegOperand<0, 1>
+                  ]>
+                ], extraSecondPreds)>,
+                !listconcat([WildcardTrue], extraProlog),
+                !listconcat([OneUse, TieReg<0, 1>], extraEpilog)>;
+
+def LUIADDI: RISCVMacroFusionCommon<[LUI], [ADDI, ADDIW]>;
+
+//===----------------------------------------------------------------------===//
----------------
dtcxzyw wrote:

Other processors may implement these macro fusions. They shouldn't be Xiangshan-specific.


https://github.com/llvm/llvm-project/pull/72362


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