[llvm] ac378ac - [RISCV][NFC] Rewrite doc comment for RISCVInstrInfo::getMemOperandWithOffsetWidth

[Alex Bradbury via llvm-commits]

Author: Alex Bradbury
Date: 2023-11-15T14:50:37Z
New Revision: ac378ac493426f8094cfaa176f1e88b62914f630

URL: https://github.com/llvm/llvm-project/commit/ac378ac493426f8094cfaa176f1e88b62914f630
DIFF: https://github.com/llvm/llvm-project/commit/ac378ac493426f8094cfaa176f1e88b62914f630.diff

LOG: [RISCV][NFC] Rewrite doc comment for RISCVInstrInfo::getMemOperandWithOffsetWidth

Attempt to clarify the expected behaviour.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 9271f807a84838b..5495d323bf17ebe 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2202,8 +2202,11 @@ MachineInstr *RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
       .setMIFlags(MemI.getFlags());
 }
 
-// Return true if get the base operand, byte offset of an instruction and the
-// memory width. Width is the size of memory that is being loaded/stored.
+// Set BaseReg (the base register operand), Offset (the byte offset being
+// accessed) and the access Width of the passed instruction that reads/writes
+// memory. Returns false if the instruction does not read/write memory or the
+// BaseReg/Offset/Width can't be determined. Is not guaranteed to always
+// recognise base operands and offsets in all cases.
 bool RISCVInstrInfo::getMemOperandWithOffsetWidth(
     const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
     unsigned &Width, const TargetRegisterInfo *TRI) const {
@@ -2212,7 +2215,7 @@ bool RISCVInstrInfo::getMemOperandWithOffsetWidth(
 
   // Here we assume the standard RISC-V ISA, which uses a base+offset
   // addressing mode. You'll need to relax these conditions to support custom
-  // load/stores instructions.
+  // load/store instructions.
   if (LdSt.getNumExplicitOperands() != 3)
     return false;
   if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm())