[llvm] [AMDGPU] - Add constant folding to s_wqm intrinsic (PR #72382)

[Jessica Del via llvm-commits]

https://github.com/OutOfCache created https://github.com/llvm/llvm-project/pull/72382

Fold any constant input to the `s_wqm` intrinsic.

>From 1864216324ccc83dd0e77287f00c62e51b07822c Mon Sep 17 00:00:00 2001
From: Jessica Del <Jessica.Del at amd.com>
Date: Wed, 15 Nov 2023 12:58:24 +0100
Subject: [PATCH] [AMDGPU] - Add constant folding to s_wqm intrinsic

Fold any constant input to the s_wqm intrinsic.
---
 llvm/lib/Analysis/ConstantFolding.cpp       | 16 ++++++++++++++++
 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll | 13 +++++--------
 2 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp
index 966a65ac26b8017..f3f0d079747e13e 100644
--- a/llvm/lib/Analysis/ConstantFolding.cpp
+++ b/llvm/lib/Analysis/ConstantFolding.cpp
@@ -1533,6 +1533,7 @@ bool llvm::canConstantFoldCallTo(const CallBase *Call, const Function *F) {
   case Intrinsic::amdgcn_perm:
   case Intrinsic::amdgcn_wave_reduce_umin:
   case Intrinsic::amdgcn_wave_reduce_umax:
+  case Intrinsic::amdgcn_s_wqm:
   case Intrinsic::arm_mve_vctp8:
   case Intrinsic::arm_mve_vctp16:
   case Intrinsic::arm_mve_vctp32:
@@ -2422,6 +2423,21 @@ static Constant *ConstantFoldScalarCall1(StringRef Name,
 
       return ConstantFP::get(Ty->getContext(), Val);
     }
+
+    case Intrinsic::amdgcn_s_wqm: {
+      uint64_t Val = Op->getZExtValue();
+      uint64_t WQM = 0;
+      uint64_t Quad = 0xF;
+      for (unsigned i = 0; i < Op->getBitWidth() / 4;
+           ++i, Val >>= 4, Quad <<= 4) {
+        if (!(Val & 0xF))
+          continue;
+
+        WQM |= Quad;
+      }
+      return ConstantInt::get(Ty, WQM);
+    }
+
     default:
       return nullptr;
     }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
index 6676dac19ba797f..e44043ffacc07d1 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
@@ -9,10 +9,9 @@ define i32 @test_s_wqm_constant_i32() {
 ; GFX11-LABEL: test_s_wqm_constant_i32:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_wqm_b32 s0, 0x85fe3a92
-; GFX11-NEXT:    v_mov_b32_e32 v0, s0
+; GFX11-NEXT:    v_mov_b32_e32 v0, 0xff00ff0f
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %br = call i32 @llvm.amdgcn.s.wqm.i32(i32 u0x85FE3A92)
+  %br = call i32 @llvm.amdgcn.s.wqm.i32(i32 u0x85003A02)
   ret i32 %br
 }
 
@@ -48,12 +47,10 @@ define i64 @test_s_wqm_constant_i64() {
 ; GFX11-LABEL: test_s_wqm_constant_i64:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, 0x85fe3a92
-; GFX11-NEXT:    s_mov_b32 s1, 0x3a9285fe
-; GFX11-NEXT:    s_wqm_b64 s[0:1], s[0:1]
-; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT:    v_mov_b32_e32 v0, 0xff00ffff
+; GFX11-NEXT:    v_mov_b32_e32 v1, 0xffff0fff
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %br = call i64 @llvm.amdgcn.s.wqm.i64(i64 u0x3A9285FE85FE3A92)
+  %br = call i64 @llvm.amdgcn.s.wqm.i64(i64 u0x12480FDBAC00753E)
   ret i64 %br
 }