[llvm] [RISCV] Implement RISCVInstrInfo::isAddImmediate (PR #72356)
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 15 02:49:13 PST 2023
================
@@ -2438,6 +2438,23 @@ MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
return It;
}
+std::optional<RegImmPair> RISCVInstrInfo::isAddImmediate(const MachineInstr &MI,
+ Register Reg) const {
+ // TODO: Handle cases where Reg is a super- or sub-register of the
+ // destination register.
+ const MachineOperand &Op0 = MI.getOperand(0);
+ if (!Op0.isReg() || Reg != Op0.getReg())
+ return std::nullopt;
+
+ // Don't consider ADDIW as a candidate because the caller may not be aware
+ // of its sign extension behaviour.
+ if (MI.getOpcode() == RISCV::ADDI && MI.getOperand(1).isReg() &&
----------------
asb wrote:
I'm not sure if we have such an instance. The AArch64 implementation is concerned that the third operand might be a global address but I haven't confirmed if that could happen for us. It just seemed sensible to code defensively.
https://github.com/llvm/llvm-project/pull/72356
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