[llvm] [RISCV] Use TableGen-based macro fusion (PR #72224)

[Wang Pengcheng via llvm-commits]

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@@ -95,6 +95,12 @@ class MCOperandPredicate<int Index> : MCInstPredicate {
 // Return true if machine operand at position `Index` is a register operand.
 class CheckIsRegOperand<int Index> : MCOperandPredicate<Index>;
 
+// Return true if machine operand at position `Index` is a virtual register operand.
+class CheckIsVRegOperand<int Index> : MCOperandPredicate<Index>;
+
+// Return true if machine operand at position `Index` is not a virtual register operand.
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wangpc-pp wrote:

It's common enough I think. We can save some characters at least. :-)
Another existed example in `llvm/include/llvm/Target/TargetInstrPredicate.td`:
```
// Check if register operand at index `Index` is the invalid register.
class CheckInvalidRegOperand<int Index> : CheckOperandBase<Index>;

// Return true if machine operand at position `Index` is a valid
// register operand.
class CheckValidRegOperand<int Index> :
  CheckNot<CheckInvalidRegOperand<Index>>;
```

https://github.com/llvm/llvm-project/pull/72224