[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 15 00:22:40 PST 2023
================
@@ -14282,10 +14379,20 @@ static SDValue performCONCAT_VECTORSCombine(SDNode *N, SelectionDAG &DAG,
static SDValue combineToVWMACC(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
- assert(N->getOpcode() == RISCVISD::ADD_VL);
+
+ assert(N->getOpcode() == RISCVISD::ADD_VL || N->getOpcode() == ISD::ADD);
+
+ if (N->getValueType(0).isFixedLengthVector())
+ return SDValue();
+
SDValue Addend = N->getOperand(0);
SDValue MulOp = N->getOperand(1);
- SDValue AddMergeOp = N->getOperand(2);
+ SDValue AddMergeOp = [](SDNode *N, SelectionDAG &DAG) {
+ if (N->getOpcode() == ISD::ADD)
+ return DAG.getUNDEF(N->getValueType(0));
+ else
----------------
qcolombet wrote:
No `else` after return.
https://github.com/llvm/llvm-project/pull/72340
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