[llvm] [X86][MC] Support decoding of EGPR for APX (PR #72102)

[Shengchen Kan via llvm-commits]

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@@ -855,8 +884,31 @@ static int fixupReg(struct InternalInstruction *insn,
     if (!valid)
       return -1;
     break;
-  case ENCODING_SIB:
   CASE_ENCODING_RM:
+    if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT &&
+        modFromModRM(insn->modRM) == 3) {
+      // EVEX_X can extend the register id to 32 for a non-GPR register that is
+      // encoded in RM.
+      // mode : MODE_64_BIT
+      //  Only 8 vector registers are available in 32 bit mode
+      // mod : 3
+      //  RM encodes a register
+      switch (op->type) {
+      case TYPE_Rv:
+      case TYPE_R8:
+      case TYPE_R16:
+      case TYPE_R32:
+      case TYPE_R64:
+        break;
+      default:
----------------
KanRobert wrote:

I think no.  `default` can help us check encoding error here. If X bit was set for TMM register, then the disassembler would report an invalid instruction.

https://github.com/llvm/llvm-project/pull/72102