[llvm] c44ac52 - [RISC][GISel] Consider ABI copies when picking register bank for G_LOAD/STORE.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 14 18:59:46 PST 2023
Author: Craig Topper
Date: 2023-11-14T18:57:08-08:00
New Revision: c44ac52e7d61d411af970896f9e617c612a74756
URL: https://github.com/llvm/llvm-project/commit/c44ac52e7d61d411af970896f9e617c612a74756
DIFF: https://github.com/llvm/llvm-project/commit/c44ac52e7d61d411af970896f9e617c612a74756.diff
LOG: [RISC][GISel] Consider ABI copies when picking register bank for G_LOAD/STORE.
This is partially based on AArch64, but reduced to handle just the case
we currently have a test for.
Added:
Modified:
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index cb1da8ff11c08cb..0777b9962468935 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -110,7 +110,9 @@ static const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
}
// TODO: Make this more like AArch64?
-static bool onlyUsesFP(const MachineInstr &MI) {
+bool RISCVRegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
+ const MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI) const {
switch (MI.getOpcode()) {
case TargetOpcode::G_FADD:
case TargetOpcode::G_FSUB:
@@ -131,11 +133,19 @@ static bool onlyUsesFP(const MachineInstr &MI) {
break;
}
+ // If we have a copy instruction, we could be feeding floating point
+ // instructions.
+ if (MI.getOpcode() == TargetOpcode::COPY)
+ return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) ==
+ &RISCV::FPRBRegBank;
+
return false;
}
// TODO: Make this more like AArch64?
-static bool onlyDefinesFP(const MachineInstr &MI) {
+bool RISCVRegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
+ const MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI) const {
switch (MI.getOpcode()) {
case TargetOpcode::G_FADD:
case TargetOpcode::G_FSUB:
@@ -156,6 +166,12 @@ static bool onlyDefinesFP(const MachineInstr &MI) {
break;
}
+ // If we have a copy instruction, we could be fed by floating point
+ // instructions.
+ if (MI.getOpcode() == TargetOpcode::COPY)
+ return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) ==
+ &RISCV::FPRBRegBank;
+
return false;
}
@@ -173,6 +189,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
+ const TargetSubtargetInfo &STI = MF.getSubtarget();
+ const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
unsigned GPRSize = getMaximumSize(RISCV::GPRBRegBankID);
assert((GPRSize == 32 || GPRSize == 64) && "Unexpected GPR size");
@@ -235,7 +253,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
// assume this was a floating point load in the IR. If it was
// not, we would have had a bitcast before reaching that
// instruction.
- return onlyUsesFP(UseMI);
+ return onlyUsesFP(UseMI, MRI, TRI);
})) {
OperandsMapping = getOperandsMapping(
{getFPValueMapping(Ty.getSizeInBits()), GPRValueMapping});
@@ -254,7 +272,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
}
MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(0).getReg());
- if (onlyDefinesFP(*DefMI)) {
+ if (onlyDefinesFP(*DefMI, MRI, TRI)) {
OperandsMapping = getOperandsMapping(
{getFPValueMapping(Ty.getSizeInBits()), GPRValueMapping});
}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
index 8b6246bb00e1f2a..c1c347884ac8e8f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
@@ -38,6 +38,15 @@ class RISCVRegisterBankInfo final : public RISCVGenRegisterBankInfo {
const InstructionMapping &
getInstrMapping(const MachineInstr &MI) const override;
+
+private:
+ /// \returns true if \p MI only uses FPRs.
+ bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI) const;
+
+ /// \returns true if \p MI only defines FPRs.
+ bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI) const;
};
} // end namespace llvm
#endif
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
index db9ee833b3b99c0..50a8faa2504f382 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
@@ -1,10 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
# RUN: -simplify-mir -verify-machineinstrs %s \
-# RUN: -o - | FileCheck %s --check-prefixes=CHECK,RV32
+# RUN: -o - | FileCheck %s --check-prefixes=CHECK
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
# RUN: -simplify-mir -verify-machineinstrs %s \
-# RUN: -o - | FileCheck %s --check-prefixes=CHECK,RV64
+# RUN: -o - | FileCheck %s --check-prefixes=CHECK
---
name: fp_store_fp_def_f32
@@ -64,22 +64,13 @@ body: |
bb.1:
liveins: $x10, $f10_d
- ; RV32-LABEL: name: fp_store_no_def_f64
- ; RV32: liveins: $x10, $f10_d
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
- ; RV32-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64))
- ; RV32-NEXT: PseudoRET
- ;
- ; RV64-LABEL: name: fp_store_no_def_f64
- ; RV64: liveins: $x10, $f10_d
- ; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
- ; RV64-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY [[COPY1]](s64)
- ; RV64-NEXT: G_STORE [[COPY2]](s64), [[COPY]](p0) :: (store (s64))
- ; RV64-NEXT: PseudoRET
+ ; CHECK-LABEL: name: fp_store_no_def_f64
+ ; CHECK: liveins: $x10, $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64))
+ ; CHECK-NEXT: PseudoRET
%0:_(p0) = COPY $x10
%1:_(s64) = COPY $f10_d
G_STORE %1(s64), %0(p0) :: (store (s64))
@@ -144,23 +135,14 @@ body: |
bb.1:
liveins: $x10, $f10_d
- ; RV32-LABEL: name: fp_load_no_use_f64
- ; RV32: liveins: $x10, $f10_d
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
- ; RV32-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
- ; RV32-NEXT: $f10_d = COPY [[LOAD]](s64)
- ; RV32-NEXT: PseudoRET implicit $f10_d
- ;
- ; RV64-LABEL: name: fp_load_no_use_f64
- ; RV64: liveins: $x10, $f10_d
- ; RV64-NEXT: {{ $}}
- ; RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
- ; RV64-NEXT: [[LOAD:%[0-9]+]]:gprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
- ; RV64-NEXT: $f10_d = COPY [[LOAD]](s64)
- ; RV64-NEXT: PseudoRET implicit $f10_d
+ ; CHECK-LABEL: name: fp_load_no_use_f64
+ ; CHECK: liveins: $x10, $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+ ; CHECK-NEXT: $f10_d = COPY [[LOAD]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
%0:_(p0) = COPY $x10
%1:_(s64) = COPY $f10_d
%2:_(s64) = G_LOAD %0(p0) :: (load (s64))
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