[llvm] [AMDGPU] Prefer lower total register usage in regions with spilling (PR #71882)

[Jeffrey Byrnes via llvm-commits]

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@@ -115,7 +119,19 @@ bool GCNRegPressure::less(const GCNSubtarget &ST,
     SGPRImportant = false;
   }
 
-  // compare large regs pressure
+  // In regions with spilling, we should give prefernce to the schedule with
+  // less general RP.
+  if (Occ <= MFI.getMinWavesPerEU()) {
+    unsigned GPRPressure =
+        SGPRImportant ? getSGPRNum() : getVGPRNum(ST.hasGFX90AInsts());
+    unsigned OtherGPRPressure =
+        SGPRImportant ? O.getSGPRNum() : O.getVGPRNum(ST.hasGFX90AInsts());
+
+    if (GPRPressure != OtherGPRPressure)
+      return GPRPressure < OtherGPRPressure;
+  }
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jrbyrnes wrote:

Hi Valery -- 

Thanks for your comments. 

This patch doesn't really intend to answer the question "which schedule to prefer" in general, but, instead, which schedule to prefer when there is spilling.

For this patch, we would like to determine which register type which is excessive / is concerning for spilling. For this purpose, I think the current determination of SGPRImportant is okay. The only default path to GCNRegPressure::less is via `mayCauseSpilling`. GCNRegPressure::less will (now) only be entered if `WavesAfter <= MFI.getMinWavesPerEU() && isRegionWithExcessRP() `. Thus, we know occupancy is concerning, and that either SGPR or VGPR pressure is excessive (I have passed the latter as a flag). The occupancy checks will pick up on which type of register is excessive -- unless there is disagreement between before / after or if they are both excessive. 



https://github.com/llvm/llvm-project/pull/71882