[llvm] [AMDGPU] RA inserted scalar instructions can be at the BB top (PR #72140)

[Stanislav Mekhanoshin via llvm-commits]

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@@ -8474,16 +8474,24 @@ unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register SrcReg,
   return AMDGPU::COPY;
 }
 
-bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI) const {
+bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,
+                                       Register Reg) const {
   // We need to handle instructions which may be inserted during register
   // allocation to handle the prolog. The initial prolog instruction may have
   // been separated from the start of the block by spills and copies inserted
-  // needed by the prolog.
+  // needed by the prolog. However, the insertions for scalar registers can
+  // always be placed at the BB top as they are independent of the exec mask
+  // value.
   uint16_t Opc = MI.getOpcode();
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rampitec wrote:

Still the whole block can be avoided if Reg is unset.

https://github.com/llvm/llvm-project/pull/72140