[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)

[Craig Topper via llvm-commits]

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@@ -2262,8 +2262,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
           }
 
           // Make sure the register fits into its register bank if any.
-          if (RegBank && Ty.isValid() &&
-              RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits()) {
+          if (RegBank && Ty.isValid() && (!Ty.isScalable() &&
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topperc wrote:

Why the extra parentheses?

https://github.com/llvm/llvm-project/pull/71541