[llvm] 506a30d - [SLP][NFC]Add a test with cast op, not matching original cast op, NFC.

Alexey Bataev via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 14 10:11:37 PST 2023


Author: Alexey Bataev
Date: 2023-11-14T10:08:12-08:00
New Revision: 506a30d30fa3cb19b4d2f04e1354cedc09925558

URL: https://github.com/llvm/llvm-project/commit/506a30d30fa3cb19b4d2f04e1354cedc09925558
DIFF: https://github.com/llvm/llvm-project/commit/506a30d30fa3cb19b4d2f04e1354cedc09925558.diff

LOG: [SLP][NFC]Add a test with cast op, not matching original cast op, NFC.

Added: 
    llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-cast.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-cast.ll b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-cast.ll
new file mode 100644
index 000000000000000..cb2d992fc0104bb
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-cast.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt --passes=slp-vectorizer -slp-threshold=-25 -mtriple=x86_64-unknown-linux-gnu -S < %s | FileCheck %s
+
+define ptr @test(i8 %0) {
+; CHECK-LABEL: define ptr @test(
+; CHECK-SAME: i8 [[TMP0:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CONV12_I:%.*]] = zext i8 [[TMP0]] to i32
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[CONV12_I]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64>
+; CHECK-NEXT:    [[TMP4:%.*]] = trunc <2 x i64> [[TMP3]] to <2 x i8>
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i8> [[TMP4]], i32 0
+; CHECK-NEXT:    [[TMP6:%.*]] = zext i8 [[TMP5]] to i64
+; CHECK-NEXT:    [[ARRAYIDX50_I:%.*]] = getelementptr i8, ptr null, i64 [[TMP6]]
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x i8> [[TMP4]], i32 1
+; CHECK-NEXT:    [[TMP8:%.*]] = zext i8 [[TMP7]] to i64
+; CHECK-NEXT:    [[ARRAYIDX16_I:%.*]] = getelementptr i8, ptr null, i64 [[TMP8]]
+; CHECK-NEXT:    ret ptr null
+;
+entry:
+  %shr48.i = lshr i32 0, 0
+  %idxprom49.i = zext nneg i32 %shr48.i to i64
+  %arrayidx50.i = getelementptr i8, ptr null, i64 %idxprom49.i
+  %conv12.i = zext i8 %0 to i32
+  %shr14.i = lshr i32 %conv12.i, 0
+  %idxprom15.i = zext nneg i32 %shr14.i to i64
+  %arrayidx16.i = getelementptr i8, ptr null, i64 %idxprom15.i
+  ret ptr null
+}


        


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