[llvm] [RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (PR #71501)

[Michael Maitland via llvm-commits]

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@@ -8,7 +8,7 @@
 define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
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michaelmaitland wrote:

If there was another vector instruction in the sequence that needed some different LMUL other than m1, then that LMUL would have been used instead of m1, since vmv.s.x and vmv.x.s has no impact on LMUL anymore. So I am not worried about the possibility of an extra vsetvli instruction being inserted.

I also don't know of any hardware that has differing performance on fractional LMUL compared to m1. For that reason, I think we could probably hold off on defaulting to the smallest-legal-fractional-for-sew in vsetvli insertion until there was a use case that made it worthwhile.

https://github.com/llvm/llvm-project/pull/71501