[llvm] [RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (PR #71501)

[Philip Reames via llvm-commits]

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@@ -8,7 +8,7 @@
 define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
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preames wrote:

I don't know of any reason to think increasing to m1 here will have any effect on known processors, but there's a lot of uncertainty here.  I will note that defaulting to smallest-legal-fractional-for-sew in insert vsetvli insertion on this instruction probably wouldn't be too painful, so we can likely reverse this easily if needed.  (Luke, might be worth playing with that just to reduce the diff.)

https://github.com/llvm/llvm-project/pull/71501