[llvm] [InstCombine] Follow-up to "When -A + B both have nsw flag, set nsw f… (PR #72282)
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Tue Nov 14 08:36:00 PST 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: None (Z572)
<details>
<summary>Changes</summary>
…lag."
In 3c037b7306f57039e24a1470687cc39a795584ac, I've miss suggested about cast.
---
Full diff: https://github.com/llvm/llvm-project/pull/72282.diff
1 Files Affected:
- (modified) llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp (+1-1)
``````````diff
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
index d390d3a581fcaa2..2bd738c95ecaa7f 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -1488,7 +1488,7 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
// -A + B --> B - A
auto *Sub = BinaryOperator::CreateSub(RHS, A);
- auto *OB0 = dyn_cast<OverflowingBinaryOperator>(LHS);
+ auto *OB0 = cast<OverflowingBinaryOperator>(LHS);
Sub->setHasNoSignedWrap(I.hasNoSignedWrap() && OB0->hasNoSignedWrap());
return Sub;
``````````
</details>
https://github.com/llvm/llvm-project/pull/72282
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