[llvm] [RISCV] Use TableGen-based macro fusion (PR #72224)

[Mikhail Gudim via llvm-commits]

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@@ -95,6 +95,12 @@ class MCOperandPredicate<int Index> : MCInstPredicate {
 // Return true if machine operand at position `Index` is a register operand.
 class CheckIsRegOperand<int Index> : MCOperandPredicate<Index>;
 
+// Return true if machine operand at position `Index` is a virtual register operand.
+class CheckIsVRegOperand<int Index> : MCOperandPredicate<Index>;
+
+// Return true if machine operand at position `Index` is not a virtual register operand.
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mgudim wrote:

why do we need this if we could just use the negation of the previous?

https://github.com/llvm/llvm-project/pull/72224