[llvm] AMDGPU/SILowerI1Copies process phi incomings in specific order (PR #72124)

[via llvm-commits]

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@@ -581,10 +587,24 @@ bool SILowerI1Copies::lowerPhis() {
         assert(IncomingDef->isPHI() || PhiRegisters.count(IncomingReg));
       }
 
-      IncomingBlocks.push_back(IncomingMBB);
-      IncomingRegs.push_back(IncomingReg);
+      Incomings.push_back({IncomingReg, IncomingMBB, Register{}});
     }
 
+    // When building merge-LaneMasks, if block A dominates block B, block A
+    // must be processed first. If there is no dominate relation order does
+    // not matter since there will be no lane mask merging.
+    // To ensure this we need to sort incomings by some criteria
+    // dominates() can't be used since it is not strict weak ordering so we use
+    // DFSNumIn, DFS visitation order for nodes in the dominator tree, from
+    // MachineDominatorTree.
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petar-avramovic wrote:

Yes, you are right. I would like to look into this again, global-isel gets register 0 as PrevReg in some cases. I will update the patch soon.

https://github.com/llvm/llvm-project/pull/72124