[llvm] c14602b - [RISCV] Add PseudoCCADDIW/SLLW/SRLW/SRAW/SLLIW/SRLIW/SRAIW to RISCVOptWInstrs.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-13T22:41:52-08:00
New Revision: c14602b318f2d439af254710095684c1f5a8a386

URL: https://github.com/llvm/llvm-project/commit/c14602b318f2d439af254710095684c1f5a8a386
DIFF: https://github.com/llvm/llvm-project/commit/c14602b318f2d439af254710095684c1f5a8a386.diff

LOG: [RISCV] Add PseudoCCADDIW/SLLW/SRLW/SRAW/SLLIW/SRLIW/SRAIW to RISCVOptWInstrs.

These can be treated simlarly to PseudoCCADDW/SUBW.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index e73cab58d7016f4..a2954b6972522b3 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -482,9 +482,16 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
 
       break;
     case RISCV::PseudoCCADDW:
+    case RISCV::PseudoCCADDIW:
     case RISCV::PseudoCCSUBW:
-      // Returns operand 4 or an ADDW/SUBW of operands 5 and 6. We only need to
-      // check if operand 4 is sign extended.
+    case RISCV::PseudoCCSLLW:
+    case RISCV::PseudoCCSRLW:
+    case RISCV::PseudoCCSRAW:
+    case RISCV::PseudoCCSLLIW:
+    case RISCV::PseudoCCSRLIW:
+    case RISCV::PseudoCCSRAIW:
+      // Returns operand 4 or an ADDW/SUBW/etc. of operands 5 and 6. We only
+      // need to check if operand 4 is sign extended.
       if (!AddRegDefToWorkList(MI->getOperand(4).getReg()))
         return false;
       break;