[llvm] [RISCV] Eliminate dead li after emitting VSETVLIs (PR #65934)

[Luke Lau via llvm-commits]

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@@ -3048,6 +3048,14 @@ bool RISCV::isZEXT_B(const MachineInstr &MI) {
          MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 255;
 }
 
+// Returns true if this is the li rd, simm12 pattern, addi rd, x0, simm12.
+bool RISCV::isLoadSImm12(const MachineInstr &MI, bool NonZero) {
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lukel97 wrote:

Do we need NonZero if it's always called with true?

https://github.com/llvm/llvm-project/pull/65934