[llvm] [RISCV][GISel] Add support for G_IS_FPCLASS in F and D extensions (PR #72000)

[Min-Yih Hsu via llvm-commits]

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@@ -948,6 +952,61 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI,
   return true;
 }
 
+bool RISCVInstructionSelector::selectIsFPClass(MachineInstr &MI,
+                                               MachineIRBuilder &MIB,
+                                               MachineRegisterInfo &MRI) const {
+  Register GISFPCLASS = MI.getOperand(0).getReg();
+  Register Src = MI.getOperand(1).getReg();
+  const MachineOperand &ImmOp = MI.getOperand(2);
+  const unsigned XLen = STI.getXLen();
+  unsigned NewOpc = MRI.getType(Src).getSizeInBits() == 32 ? RISCV::FCLASS_S
+                                                           : RISCV::FCLASS_D;
+
+  // Turn LLVM IR's floating point classes to that in RISC-V,
+  // by simply rotating the 10-bit immediate right by two bits.
+  APInt GFpClassImm(10, static_cast<uint64_t>(ImmOp.getImm()));
+  APInt FClassMask = GFpClassImm.rotr(2).zext(XLen);
+
+  Register FClassResult = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+  // Insert FCLASS_S/D.
+  auto FClass = MIB.buildInstr(NewOpc, {FClassResult}, {Src});
+  if (!FClass.constrainAllUses(TII, TRI, RBI))
+    return false;
+
+  if (FClassMask == 1) {
+    // We don't need to generate additional instructions if Mask is 1, as the
+    // `ANDI rs, 1` that follows will suffice.
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mshockwave wrote:

> I think we have to make an ANDI. It's not guaranteed to exist. If computeKnownBits ran on the G_ISFPCLASS, it would know that G_ISFPCLASS produces 0/1 and delete any existing ANDI.

Done

https://github.com/llvm/llvm-project/pull/72000