[llvm] [NFC][CodeGen] clang-format RegAllocFast.cpp (PR #72199)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 13 18:59:03 PST 2023
https://github.com/HaohaiWen created https://github.com/llvm/llvm-project/pull/72199
None
>From e7a1096e9d8903c6cd2e7cb70b14c29591e0591b Mon Sep 17 00:00:00 2001
From: Haohai Wen <haohai.wen at intel.com>
Date: Tue, 14 Nov 2023 10:51:49 +0800
Subject: [PATCH] [NFC][CodeGen] clang-format RegAllocFast.cpp
---
llvm/lib/CodeGen/RegAllocFast.cpp | 488 +++++++++++++++---------------
1 file changed, 237 insertions(+), 251 deletions(-)
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index 9f3c17e2799ceae..b216d7296446262 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -50,251 +50,248 @@ using namespace llvm;
#define DEBUG_TYPE "regalloc"
STATISTIC(NumStores, "Number of stores added");
-STATISTIC(NumLoads , "Number of loads added");
+STATISTIC(NumLoads, "Number of loads added");
STATISTIC(NumCoalesced, "Number of copies coalesced");
// FIXME: Remove this switch when all testcases are fixed!
static cl::opt<bool> IgnoreMissingDefs("rafast-ignore-missing-defs",
cl::Hidden);
-static RegisterRegAlloc
- fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
+static RegisterRegAlloc fastRegAlloc("fast", "fast register allocator",
+ createFastRegisterAllocator);
namespace {
- class RegAllocFast : public MachineFunctionPass {
- public:
- static char ID;
+class RegAllocFast : public MachineFunctionPass {
+public:
+ static char ID;
- RegAllocFast(const RegClassFilterFunc F = allocateAllRegClasses,
- bool ClearVirtRegs_ = true) :
- MachineFunctionPass(ID),
- ShouldAllocateClass(F),
- StackSlotForVirtReg(-1),
- ClearVirtRegs(ClearVirtRegs_) {
- }
+ RegAllocFast(const RegClassFilterFunc F = allocateAllRegClasses,
+ bool ClearVirtRegs_ = true)
+ : MachineFunctionPass(ID), ShouldAllocateClass(F),
+ StackSlotForVirtReg(-1), ClearVirtRegs(ClearVirtRegs_) {}
- private:
- MachineFrameInfo *MFI = nullptr;
- MachineRegisterInfo *MRI = nullptr;
- const TargetRegisterInfo *TRI = nullptr;
- const TargetInstrInfo *TII = nullptr;
- RegisterClassInfo RegClassInfo;
- const RegClassFilterFunc ShouldAllocateClass;
+private:
+ MachineFrameInfo *MFI = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ RegisterClassInfo RegClassInfo;
+ const RegClassFilterFunc ShouldAllocateClass;
- /// Basic block currently being allocated.
- MachineBasicBlock *MBB = nullptr;
+ /// Basic block currently being allocated.
+ MachineBasicBlock *MBB = nullptr;
- /// Maps virtual regs to the frame index where these values are spilled.
- IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
+ /// Maps virtual regs to the frame index where these values are spilled.
+ IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
- bool ClearVirtRegs;
+ bool ClearVirtRegs;
- /// Everything we know about a live virtual register.
- struct LiveReg {
- MachineInstr *LastUse = nullptr; ///< Last instr to use reg.
- Register VirtReg; ///< Virtual register number.
- MCPhysReg PhysReg = 0; ///< Currently held here.
- bool LiveOut = false; ///< Register is possibly live out.
- bool Reloaded = false; ///< Register was reloaded.
- bool Error = false; ///< Could not allocate.
+ /// Everything we know about a live virtual register.
+ struct LiveReg {
+ MachineInstr *LastUse = nullptr; ///< Last instr to use reg.
+ Register VirtReg; ///< Virtual register number.
+ MCPhysReg PhysReg = 0; ///< Currently held here.
+ bool LiveOut = false; ///< Register is possibly live out.
+ bool Reloaded = false; ///< Register was reloaded.
+ bool Error = false; ///< Could not allocate.
- explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {}
+ explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {}
- unsigned getSparseSetIndex() const {
- return Register::virtReg2Index(VirtReg);
- }
- };
-
- using LiveRegMap = SparseSet<LiveReg, identity<unsigned>, uint16_t>;
- /// This map contains entries for each virtual register that is currently
- /// available in a physical register.
- LiveRegMap LiveVirtRegs;
-
- /// Stores assigned virtual registers present in the bundle MI.
- DenseMap<Register, MCPhysReg> BundleVirtRegsMap;
-
- DenseMap<unsigned, SmallVector<MachineOperand *, 2>> LiveDbgValueMap;
- /// List of DBG_VALUE that we encountered without the vreg being assigned
- /// because they were placed after the last use of the vreg.
- DenseMap<unsigned, SmallVector<MachineInstr *, 1>> DanglingDbgValues;
-
- /// Has a bit set for every virtual register for which it was determined
- /// that it is alive across blocks.
- BitVector MayLiveAcrossBlocks;
-
- /// State of a register unit.
- enum RegUnitState {
- /// A free register is not currently in use and can be allocated
- /// immediately without checking aliases.
- regFree,
-
- /// A pre-assigned register has been assigned before register allocation
- /// (e.g., setting up a call parameter).
- regPreAssigned,
-
- /// Used temporarily in reloadAtBegin() to mark register units that are
- /// live-in to the basic block.
- regLiveIn,
-
- /// A register state may also be a virtual register number, indication
- /// that the physical register is currently allocated to a virtual
- /// register. In that case, LiveVirtRegs contains the inverse mapping.
- };
-
- /// Maps each physical register to a RegUnitState enum or virtual register.
- std::vector<unsigned> RegUnitStates;
-
- SmallVector<MachineInstr *, 32> Coalesced;
-
- using RegUnitSet = SparseSet<uint16_t, identity<uint16_t>>;
- /// Set of register units that are used in the current instruction, and so
- /// cannot be allocated.
- RegUnitSet UsedInInstr;
- RegUnitSet PhysRegUses;
- SmallVector<uint16_t, 8> DefOperandIndexes;
- // Register masks attached to the current instruction.
- SmallVector<const uint32_t *> RegMasks;
-
- void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
- bool isPhysRegFree(MCPhysReg PhysReg) const;
-
- /// Mark a physreg as used in this instruction.
- void markRegUsedInInstr(MCPhysReg PhysReg) {
- for (MCRegUnit Unit : TRI->regunits(PhysReg))
- UsedInInstr.insert(Unit);
+ unsigned getSparseSetIndex() const {
+ return Register::virtReg2Index(VirtReg);
}
+ };
- // Check if physreg is clobbered by instruction's regmask(s).
- bool isClobberedByRegMasks(MCPhysReg PhysReg) const {
- return llvm::any_of(RegMasks, [PhysReg](const uint32_t *Mask) {
- return MachineOperand::clobbersPhysReg(Mask, PhysReg);
- });
- }
+ using LiveRegMap = SparseSet<LiveReg, identity<unsigned>, uint16_t>;
+ /// This map contains entries for each virtual register that is currently
+ /// available in a physical register.
+ LiveRegMap LiveVirtRegs;
+
+ /// Stores assigned virtual registers present in the bundle MI.
+ DenseMap<Register, MCPhysReg> BundleVirtRegsMap;
+
+ DenseMap<unsigned, SmallVector<MachineOperand *, 2>> LiveDbgValueMap;
+ /// List of DBG_VALUE that we encountered without the vreg being assigned
+ /// because they were placed after the last use of the vreg.
+ DenseMap<unsigned, SmallVector<MachineInstr *, 1>> DanglingDbgValues;
+
+ /// Has a bit set for every virtual register for which it was determined
+ /// that it is alive across blocks.
+ BitVector MayLiveAcrossBlocks;
+
+ /// State of a register unit.
+ enum RegUnitState {
+ /// A free register is not currently in use and can be allocated
+ /// immediately without checking aliases.
+ regFree,
+
+ /// A pre-assigned register has been assigned before register allocation
+ /// (e.g., setting up a call parameter).
+ regPreAssigned,
+
+ /// Used temporarily in reloadAtBegin() to mark register units that are
+ /// live-in to the basic block.
+ regLiveIn,
+
+ /// A register state may also be a virtual register number, indication
+ /// that the physical register is currently allocated to a virtual
+ /// register. In that case, LiveVirtRegs contains the inverse mapping.
+ };
+
+ /// Maps each physical register to a RegUnitState enum or virtual register.
+ std::vector<unsigned> RegUnitStates;
+
+ SmallVector<MachineInstr *, 32> Coalesced;
+
+ using RegUnitSet = SparseSet<uint16_t, identity<uint16_t>>;
+ /// Set of register units that are used in the current instruction, and so
+ /// cannot be allocated.
+ RegUnitSet UsedInInstr;
+ RegUnitSet PhysRegUses;
+ SmallVector<uint16_t, 8> DefOperandIndexes;
+ // Register masks attached to the current instruction.
+ SmallVector<const uint32_t *> RegMasks;
+
+ void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
+ bool isPhysRegFree(MCPhysReg PhysReg) const;
- /// Check if a physreg or any of its aliases are used in this instruction.
- bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const {
- if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg))
+ /// Mark a physreg as used in this instruction.
+ void markRegUsedInInstr(MCPhysReg PhysReg) {
+ for (MCRegUnit Unit : TRI->regunits(PhysReg))
+ UsedInInstr.insert(Unit);
+ }
+
+ // Check if physreg is clobbered by instruction's regmask(s).
+ bool isClobberedByRegMasks(MCPhysReg PhysReg) const {
+ return llvm::any_of(RegMasks, [PhysReg](const uint32_t *Mask) {
+ return MachineOperand::clobbersPhysReg(Mask, PhysReg);
+ });
+ }
+
+ /// Check if a physreg or any of its aliases are used in this instruction.
+ bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const {
+ if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg))
+ return true;
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ if (UsedInInstr.count(Unit))
+ return true;
+ if (LookAtPhysRegUses && PhysRegUses.count(Unit))
return true;
- for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
- if (UsedInInstr.count(Unit))
- return true;
- if (LookAtPhysRegUses && PhysRegUses.count(Unit))
- return true;
- }
- return false;
}
+ return false;
+ }
- /// Mark physical register as being used in a register use operand.
- /// This is only used by the special livethrough handling code.
- void markPhysRegUsedInInstr(MCPhysReg PhysReg) {
- for (MCRegUnit Unit : TRI->regunits(PhysReg))
- PhysRegUses.insert(Unit);
- }
+ /// Mark physical register as being used in a register use operand.
+ /// This is only used by the special livethrough handling code.
+ void markPhysRegUsedInInstr(MCPhysReg PhysReg) {
+ for (MCRegUnit Unit : TRI->regunits(PhysReg))
+ PhysRegUses.insert(Unit);
+ }
- /// Remove mark of physical register being used in the instruction.
- void unmarkRegUsedInInstr(MCPhysReg PhysReg) {
- for (MCRegUnit Unit : TRI->regunits(PhysReg))
- UsedInInstr.erase(Unit);
- }
+ /// Remove mark of physical register being used in the instruction.
+ void unmarkRegUsedInInstr(MCPhysReg PhysReg) {
+ for (MCRegUnit Unit : TRI->regunits(PhysReg))
+ UsedInInstr.erase(Unit);
+ }
- enum : unsigned {
- spillClean = 50,
- spillDirty = 100,
- spillPrefBonus = 20,
- spillImpossible = ~0u
- };
+ enum : unsigned {
+ spillClean = 50,
+ spillDirty = 100,
+ spillPrefBonus = 20,
+ spillImpossible = ~0u
+ };
- public:
- StringRef getPassName() const override { return "Fast Register Allocator"; }
+public:
+ StringRef getPassName() const override { return "Fast Register Allocator"; }
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.setPreservesCFG();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
- MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoPHIs);
- }
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::NoPHIs);
+ }
- MachineFunctionProperties getSetProperties() const override {
- if (ClearVirtRegs) {
- return MachineFunctionProperties().set(
+ MachineFunctionProperties getSetProperties() const override {
+ if (ClearVirtRegs) {
+ return MachineFunctionProperties().set(
MachineFunctionProperties::Property::NoVRegs);
- }
-
- return MachineFunctionProperties();
}
- MachineFunctionProperties getClearedProperties() const override {
- return MachineFunctionProperties().set(
+ return MachineFunctionProperties();
+ }
+
+ MachineFunctionProperties getClearedProperties() const override {
+ return MachineFunctionProperties().set(
MachineFunctionProperties::Property::IsSSA);
- }
+ }
- private:
- bool runOnMachineFunction(MachineFunction &MF) override;
+private:
+ bool runOnMachineFunction(MachineFunction &MF) override;
- void allocateBasicBlock(MachineBasicBlock &MBB);
+ void allocateBasicBlock(MachineBasicBlock &MBB);
- void addRegClassDefCounts(std::vector<unsigned> &RegClassDefCounts,
- Register Reg) const;
+ void addRegClassDefCounts(std::vector<unsigned> &RegClassDefCounts,
+ Register Reg) const;
- void findAndSortDefOperandIndexes(const MachineInstr &MI);
+ void findAndSortDefOperandIndexes(const MachineInstr &MI);
- void allocateInstruction(MachineInstr &MI);
- void handleDebugValue(MachineInstr &MI);
- void handleBundle(MachineInstr &MI);
+ void allocateInstruction(MachineInstr &MI);
+ void handleDebugValue(MachineInstr &MI);
+ void handleBundle(MachineInstr &MI);
- bool usePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
- bool definePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
- bool displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
- void freePhysReg(MCPhysReg PhysReg);
+ bool usePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
+ bool definePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
+ bool displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
+ void freePhysReg(MCPhysReg PhysReg);
- unsigned calcSpillCost(MCPhysReg PhysReg) const;
+ unsigned calcSpillCost(MCPhysReg PhysReg) const;
- LiveRegMap::iterator findLiveVirtReg(Register VirtReg) {
- return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
- }
+ LiveRegMap::iterator findLiveVirtReg(Register VirtReg) {
+ return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
+ }
- LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const {
- return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
- }
+ LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const {
+ return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
+ }
- void assignVirtToPhysReg(MachineInstr &MI, LiveReg &, MCPhysReg PhysReg);
- void allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint,
- bool LookAtPhysRegUses = false);
- void allocVirtRegUndef(MachineOperand &MO);
- void assignDanglingDebugValues(MachineInstr &Def, Register VirtReg,
- MCPhysReg Reg);
- bool defineLiveThroughVirtReg(MachineInstr &MI, unsigned OpNum,
- Register VirtReg);
- bool defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
- bool LookAtPhysRegUses = false);
- bool useVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg);
-
- MachineBasicBlock::iterator
- getMBBBeginInsertionPoint(MachineBasicBlock &MBB,
- SmallSet<Register, 2> &PrologLiveIns) const;
-
- void reloadAtBegin(MachineBasicBlock &MBB);
- bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
-
- Register traceCopies(Register VirtReg) const;
- Register traceCopyChain(Register Reg) const;
-
- bool shouldAllocateRegister(const Register Reg) const;
- int getStackSpaceFor(Register VirtReg);
- void spill(MachineBasicBlock::iterator Before, Register VirtReg,
- MCPhysReg AssignedReg, bool Kill, bool LiveOut);
- void reload(MachineBasicBlock::iterator Before, Register VirtReg,
- MCPhysReg PhysReg);
-
- bool mayLiveOut(Register VirtReg);
- bool mayLiveIn(Register VirtReg);
-
- void dumpState() const;
- };
+ void assignVirtToPhysReg(MachineInstr &MI, LiveReg &, MCPhysReg PhysReg);
+ void allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint,
+ bool LookAtPhysRegUses = false);
+ void allocVirtRegUndef(MachineOperand &MO);
+ void assignDanglingDebugValues(MachineInstr &Def, Register VirtReg,
+ MCPhysReg Reg);
+ bool defineLiveThroughVirtReg(MachineInstr &MI, unsigned OpNum,
+ Register VirtReg);
+ bool defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
+ bool LookAtPhysRegUses = false);
+ bool useVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg);
+
+ MachineBasicBlock::iterator
+ getMBBBeginInsertionPoint(MachineBasicBlock &MBB,
+ SmallSet<Register, 2> &PrologLiveIns) const;
+
+ void reloadAtBegin(MachineBasicBlock &MBB);
+ bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
+
+ Register traceCopies(Register VirtReg) const;
+ Register traceCopyChain(Register Reg) const;
+
+ bool shouldAllocateRegister(const Register Reg) const;
+ int getStackSpaceFor(Register VirtReg);
+ void spill(MachineBasicBlock::iterator Before, Register VirtReg,
+ MCPhysReg AssignedReg, bool Kill, bool LiveOut);
+ void reload(MachineBasicBlock::iterator Before, Register VirtReg,
+ MCPhysReg PhysReg);
+
+ bool mayLiveOut(Register VirtReg);
+ bool mayLiveIn(Register VirtReg);
+
+ void dumpState() const;
+};
} // end anonymous namespace
@@ -431,8 +428,8 @@ bool RegAllocFast::mayLiveIn(Register VirtReg) {
/// DBG_VALUEs with \p VirtReg operands with the stack slot.
void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg,
MCPhysReg AssignedReg, bool Kill, bool LiveOut) {
- LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI)
- << " in " << printReg(AssignedReg, TRI));
+ LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) << " in "
+ << printReg(AssignedReg, TRI));
int FI = getStackSpaceFor(VirtReg);
LLVM_DEBUG(dbgs() << " to stack slot #" << FI << '\n');
@@ -503,9 +500,8 @@ void RegAllocFast::reload(MachineBasicBlock::iterator Before, Register VirtReg,
/// This is not just MBB.begin() because surprisingly we have EH_LABEL
/// instructions marking the begin of a basic block. This means we must insert
/// new instructions after such labels...
-MachineBasicBlock::iterator
-RegAllocFast::getMBBBeginInsertionPoint(
- MachineBasicBlock &MBB, SmallSet<Register, 2> &PrologLiveIns) const {
+MachineBasicBlock::iterator RegAllocFast::getMBBBeginInsertionPoint(
+ MachineBasicBlock &MBB, SmallSet<Register, 2> &PrologLiveIns) const {
MachineBasicBlock::iterator I = MBB.begin();
while (I != MBB.end()) {
if (I->isLabel()) {
@@ -542,13 +538,12 @@ void RegAllocFast::reloadAtBegin(MachineBasicBlock &MBB) {
setPhysRegState(Reg, regLiveIn);
}
-
SmallSet<Register, 2> PrologLiveIns;
// The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
// of spilling here is deterministic, if arbitrary.
- MachineBasicBlock::iterator InsertBefore
- = getMBBBeginInsertionPoint(MBB, PrologLiveIns);
+ MachineBasicBlock::iterator InsertBefore =
+ getMBBBeginInsertionPoint(MBB, PrologLiveIns);
for (const LiveReg &LR : LiveVirtRegs) {
MCPhysReg PhysReg = LR.PhysReg;
if (PhysReg == 0)
@@ -634,12 +629,12 @@ void RegAllocFast::freePhysReg(MCPhysReg PhysReg) {
setPhysRegState(PhysReg, regFree);
return;
default: {
- LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
- assert(LRI != LiveVirtRegs.end());
- LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n');
- setPhysRegState(LRI->PhysReg, regFree);
- LRI->PhysReg = 0;
- }
+ LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
+ assert(LRI != LiveVirtRegs.end());
+ LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n');
+ setPhysRegState(LRI->PhysReg, regFree);
+ LRI->PhysReg = 0;
+ }
return;
}
}
@@ -673,7 +668,7 @@ void RegAllocFast::assignDanglingDebugValues(MachineInstr &Definition,
if (UDBGValIter == DanglingDbgValues.end())
return;
- SmallVectorImpl<MachineInstr*> &Dangling = UDBGValIter->second;
+ SmallVectorImpl<MachineInstr *> &Dangling = UDBGValIter->second;
for (MachineInstr *DbgValue : Dangling) {
assert(DbgValue->isDebugValue());
if (!DbgValue->hasDebugOperandForReg(VirtReg))
@@ -683,10 +678,11 @@ void RegAllocFast::assignDanglingDebugValues(MachineInstr &Definition,
MCPhysReg SetToReg = Reg;
unsigned Limit = 20;
for (MachineBasicBlock::iterator I = std::next(Definition.getIterator()),
- E = DbgValue->getIterator(); I != E; ++I) {
+ E = DbgValue->getIterator();
+ I != E; ++I) {
if (I->modifiesRegister(Reg, TRI) || --Limit == 0) {
LLVM_DEBUG(dbgs() << "Register did not survive for " << *DbgValue
- << '\n');
+ << '\n');
SetToReg = 0;
break;
}
@@ -716,9 +712,7 @@ void RegAllocFast::assignVirtToPhysReg(MachineInstr &AtMI, LiveReg &LR,
assignDanglingDebugValues(AtMI, VirtReg, PhysReg);
}
-static bool isCoalescable(const MachineInstr &MI) {
- return MI.isFullCopy();
-}
+static bool isCoalescable(const MachineInstr &MI) { return MI.isFullCopy(); }
Register RegAllocFast::traceCopyChain(Register Reg) const {
static const unsigned ChainLengthLimit = 3;
@@ -757,8 +751,8 @@ Register RegAllocFast::traceCopies(Register VirtReg) const {
}
/// Allocates a physical register for VirtReg.
-void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR,
- Register Hint0, bool LookAtPhysRegUses) {
+void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint0,
+ bool LookAtPhysRegUses) {
const Register VirtReg = LR.VirtReg;
assert(LR.PhysReg == 0);
@@ -784,7 +778,6 @@ void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR,
Hint0 = Register();
}
-
// Try other hint.
Register Hint1 = traceCopies(VirtReg);
if (Hint1.isPhysical() && MRI->isAllocatable(Hint1) && RC.contains(Hint1) &&
@@ -792,12 +785,12 @@ void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR,
// Take hint if the register is currently free.
if (isPhysRegFree(Hint1)) {
LLVM_DEBUG(dbgs() << "\tPreferred Register 0: " << printReg(Hint1, TRI)
- << '\n');
+ << '\n');
assignVirtToPhysReg(MI, LR, Hint1);
return;
} else {
LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint1, TRI)
- << " occupied\n");
+ << " occupied\n");
}
} else {
Hint1 = Register();
@@ -891,12 +884,12 @@ bool RegAllocFast::defineLiveThroughVirtReg(MachineInstr &MI, unsigned OpNum,
LRI->PhysReg = 0;
allocVirtReg(MI, *LRI, 0, true);
MachineBasicBlock::iterator InsertBefore =
- std::next((MachineBasicBlock::iterator)MI.getIterator());
+ std::next((MachineBasicBlock::iterator)MI.getIterator());
LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to "
<< printReg(PrevReg, TRI) << '\n');
BuildMI(*MBB, InsertBefore, MI.getDebugLoc(),
TII->get(TargetOpcode::COPY), PrevReg)
- .addReg(LRI->PhysReg, llvm::RegState::Kill);
+ .addReg(LRI->PhysReg, llvm::RegState::Kill);
}
MachineOperand &MO = MI.getOperand(OpNum);
if (MO.getSubReg() && !MO.isUndef()) {
@@ -956,8 +949,8 @@ bool RegAllocFast::defineVirtReg(MachineInstr &MI, unsigned OpNum,
if (!MI.isImplicitDef()) {
MachineBasicBlock::iterator SpillBefore =
std::next((MachineBasicBlock::iterator)MI.getIterator());
- LLVM_DEBUG(dbgs() << "Spill Reason: LO: " << LRI->LiveOut << " RL: "
- << LRI->Reloaded << '\n');
+ LLVM_DEBUG(dbgs() << "Spill Reason: LO: " << LRI->LiveOut
+ << " RL: " << LRI->Reloaded << '\n');
bool Kill = LRI->LastUse == nullptr;
spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);
@@ -969,8 +962,8 @@ bool RegAllocFast::defineVirtReg(MachineInstr &MI, unsigned OpNum,
for (MachineOperand &MO : MI.operands()) {
if (MO.isMBB()) {
MachineBasicBlock *Succ = MO.getMBB();
- TII->storeRegToStackSlot(*Succ, Succ->begin(), PhysReg, Kill,
- FI, &RC, TRI, VirtReg);
+ TII->storeRegToStackSlot(*Succ, Succ->begin(), PhysReg, Kill, FI,
+ &RC, TRI, VirtReg);
++NumStores;
Succ->addLiveIn(PhysReg);
}
@@ -1106,8 +1099,10 @@ void RegAllocFast::dumpState() const {
assert(I != LiveVirtRegs.end() && "have LiveVirtRegs entry");
if (I->LiveOut || I->Reloaded) {
dbgs() << '[';
- if (I->LiveOut) dbgs() << 'O';
- if (I->Reloaded) dbgs() << 'R';
+ if (I->LiveOut)
+ dbgs() << 'O';
+ if (I->Reloaded)
+ dbgs() << 'R';
dbgs() << ']';
}
assert(TRI->hasRegUnit(I->PhysReg, Unit) && "inverse mapping present");
@@ -1122,8 +1117,7 @@ void RegAllocFast::dumpState() const {
assert(VirtReg.isVirtual() && "Bad map key");
MCPhysReg PhysReg = LR.PhysReg;
if (PhysReg != 0) {
- assert(Register::isPhysicalRegister(PhysReg) &&
- "mapped to physreg");
+ assert(Register::isPhysicalRegister(PhysReg) && "mapped to physreg");
for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
assert(RegUnitStates[Unit] == VirtReg && "inverse map valid");
}
@@ -1133,8 +1127,8 @@ void RegAllocFast::dumpState() const {
#endif
/// Count number of defs consumed from each register class by \p Reg
-void RegAllocFast::addRegClassDefCounts(std::vector<unsigned> &RegClassDefCounts,
- Register Reg) const {
+void RegAllocFast::addRegClassDefCounts(
+ std::vector<unsigned> &RegClassDefCounts, Register Reg) const {
assert(RegClassDefCounts.size() == TRI->getNumRegClasses());
if (Reg.isVirtual()) {
@@ -1586,10 +1580,7 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) {
// Traverse block in reverse order allocating instructions one by one.
for (MachineInstr &MI : reverse(MBB)) {
- LLVM_DEBUG(
- dbgs() << "\n>> " << MI << "Regs:";
- dumpState()
- );
+ LLVM_DEBUG(dbgs() << "\n>> " << MI << "Regs:"; dumpState());
// Special handling for debug values. Note that they are not allowed to
// affect codegen of the other instructions in any way.
@@ -1607,10 +1598,7 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) {
}
}
- LLVM_DEBUG(
- dbgs() << "Begin Regs:";
- dumpState()
- );
+ LLVM_DEBUG(dbgs() << "Begin Regs:"; dumpState());
// Spill all physical registers holding virtual registers now.
LLVM_DEBUG(dbgs() << "Loading live registers at begin of block.\n");
@@ -1629,7 +1617,7 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) {
if (!DbgValue->hasDebugOperandForReg(UDBGPair.first))
continue;
LLVM_DEBUG(dbgs() << "Register did not survive for " << *DbgValue
- << '\n');
+ << '\n');
DbgValue->setDebugValueUndef();
}
}
@@ -1677,9 +1665,7 @@ bool RegAllocFast::runOnMachineFunction(MachineFunction &MF) {
return true;
}
-FunctionPass *llvm::createFastRegisterAllocator() {
- return new RegAllocFast();
-}
+FunctionPass *llvm::createFastRegisterAllocator() { return new RegAllocFast(); }
FunctionPass *llvm::createFastRegisterAllocator(RegClassFilterFunc Ftor,
bool ClearVirtRegs) {
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