[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)

[Matt Arsenault via llvm-commits]

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@@ -14,3 +14,15 @@ def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
 
 /// Floating Point Registers: F.
 def FPRRegBank : RegisterBank<"FPRB", [FPR64]>;
+
+/// Vector Register Banks:
+def VRRegBank : RegisterBank<"VRB", [VR]>;
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arsenm wrote:

Register banks are specifically vaguer than register classes. They are supposed to express how expensive and/or impossible it is to copy between registers of a class. e.g. it might be expensive to copy values between GPRs and FPRs, but the bank doesn't need to concern itself with the specific operand constraints of individual instructions 

https://github.com/llvm/llvm-project/pull/71541