[llvm] 915e092 - [RISCV] Select zext as sext when sign bit is 0 for -riscv-experimental-rv64-legal-i32
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 13 12:29:01 PST 2023
Author: Craig Topper
Date: 2023-11-13T12:21:36-08:00
New Revision: 915e092400f92a617a4ca7cb9f03a642bb30c7cc
URL: https://github.com/llvm/llvm-project/commit/915e092400f92a617a4ca7cb9f03a642bb30c7cc
DIFF: https://github.com/llvm/llvm-project/commit/915e092400f92a617a4ca7cb9f03a642bb30c7cc.diff
LOG: [RISCV] Select zext as sext when sign bit is 0 for -riscv-experimental-rv64-legal-i32
In our default SelectionDAG where i32 isn't legal, the zext will become
and i64 AND and often get optimized out on its own. With i32 legal, we
need to turn it in into sext.w and rely on RISCVOptWInstrs to remove it.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 84e2bdd4fbbbd72..af34e026bed1488 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2014,6 +2014,11 @@ def as_i64imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
}]>;
+def zext_is_sext : PatFrag<(ops node:$src), (zext node:$src), [{
+ KnownBits Known = CurDAG->computeKnownBits(N->getOperand(0), 0);
+ return Known.isNonNegative();
+}]>;
+
let Predicates = [IsRV64] in {
def : LdPat<sextloadi8, LB, i32>;
def : LdPat<extloadi8, LBU, i32>; // Prefer unsigned due to no c.lb in Zcb.
@@ -2054,6 +2059,9 @@ def : PatGprImm<sra, SRAIW, uimm5, i32>;
def : Pat<(i32 (and GPR:$rs, TrailingOnesMask:$mask)),
(SRLI (SLLI $rs, (i64 (XLenSubTrailingOnes $mask))),
(i64 (XLenSubTrailingOnes $mask)))>;
+
+// Use sext if the sign bit of the input is 0.
+def : Pat<(zext_is_sext GPR:$src), (ADDIW GPR:$src, 0)>;
}
let Predicates = [IsRV64, NotHasStdExtZba] in {
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
index 25415c8e09ecbae..3e2e6ac75af8311 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
@@ -302,8 +302,6 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64XTHEADBB-LABEL: ctlz_lshr_i32:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srliw a0, a0, 1
-; RV64XTHEADBB-NEXT: slli a0, a0, 32
-; RV64XTHEADBB-NEXT: srli a0, a0, 32
; RV64XTHEADBB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NEXT: addi a0, a0, -32
; RV64XTHEADBB-NEXT: ret
@@ -392,8 +390,6 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: srliw a0, a0, 27
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0)
; RV64I-NEXT: add a0, a1, a0
@@ -417,8 +413,6 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
; RV64XTHEADBB-NEXT: addiw a1, a1, 1329
; RV64XTHEADBB-NEXT: call __muldi3 at plt
; RV64XTHEADBB-NEXT: srliw a0, a0, 27
-; RV64XTHEADBB-NEXT: slli a0, a0, 32
-; RV64XTHEADBB-NEXT: srli a0, a0, 32
; RV64XTHEADBB-NEXT: lui a1, %hi(.LCPI6_0)
; RV64XTHEADBB-NEXT: addi a1, a1, %lo(.LCPI6_0)
; RV64XTHEADBB-NEXT: add a0, a1, a0
@@ -448,8 +442,6 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: srliw a0, a0, 27
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: lui a1, %hi(.LCPI7_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_0)
; RV64I-NEXT: add a0, a1, a0
@@ -468,8 +460,6 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64XTHEADBB-NEXT: addiw a1, a1, 1329
; RV64XTHEADBB-NEXT: call __muldi3 at plt
; RV64XTHEADBB-NEXT: srliw a0, a0, 27
-; RV64XTHEADBB-NEXT: slli a0, a0, 32
-; RV64XTHEADBB-NEXT: srli a0, a0, 32
; RV64XTHEADBB-NEXT: lui a1, %hi(.LCPI7_0)
; RV64XTHEADBB-NEXT: addi a1, a1, %lo(.LCPI7_0)
; RV64XTHEADBB-NEXT: add a0, a1, a0
@@ -494,8 +484,6 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: srliw a0, a0, 27
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: lui a1, %hi(.LCPI8_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI8_0)
; RV64I-NEXT: add a0, a1, a0
@@ -520,8 +508,6 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64XTHEADBB-NEXT: addiw a1, a1, 1329
; RV64XTHEADBB-NEXT: call __muldi3 at plt
; RV64XTHEADBB-NEXT: srliw a0, a0, 27
-; RV64XTHEADBB-NEXT: slli a0, a0, 32
-; RV64XTHEADBB-NEXT: srli a0, a0, 32
; RV64XTHEADBB-NEXT: lui a1, %hi(.LCPI8_0)
; RV64XTHEADBB-NEXT: addi a1, a1, %lo(.LCPI8_0)
; RV64XTHEADBB-NEXT: add a0, a1, a0
@@ -552,8 +538,6 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: srliw a0, a0, 27
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: lui a1, %hi(.LCPI9_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0)
; RV64I-NEXT: add a0, a1, a0
@@ -581,8 +565,6 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64XTHEADBB-NEXT: addiw a1, a1, 1329
; RV64XTHEADBB-NEXT: call __muldi3 at plt
; RV64XTHEADBB-NEXT: srliw a0, a0, 27
-; RV64XTHEADBB-NEXT: slli a0, a0, 32
-; RV64XTHEADBB-NEXT: srli a0, a0, 32
; RV64XTHEADBB-NEXT: lui a1, %hi(.LCPI9_0)
; RV64XTHEADBB-NEXT: addi a1, a1, %lo(.LCPI9_0)
; RV64XTHEADBB-NEXT: add a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
index c15bc8b10f80200..06bebb29a04b927 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
@@ -1521,7 +1521,6 @@ define signext i32 @srliw_1_sh2add(ptr %0, i32 signext %1) {
; RV64ZBA-LABEL: srliw_1_sh2add:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: srliw a1, a1, 1
-; RV64ZBA-NEXT: zext.w a1, a1
; RV64ZBA-NEXT: sh2add a0, a1, a0
; RV64ZBA-NEXT: lw a0, 0(a0)
; RV64ZBA-NEXT: ret
@@ -1545,7 +1544,6 @@ define i64 @srliw_1_sh3add(ptr %0, i32 signext %1) {
; RV64ZBA-LABEL: srliw_1_sh3add:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: srliw a1, a1, 1
-; RV64ZBA-NEXT: zext.w a1, a1
; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64ZBA-NEXT: ld a0, 0(a0)
; RV64ZBA-NEXT: ret
@@ -1569,7 +1567,6 @@ define i64 @srliw_2_sh3add(ptr %0, i32 signext %1) {
; RV64ZBA-LABEL: srliw_2_sh3add:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: srliw a1, a1, 2
-; RV64ZBA-NEXT: zext.w a1, a1
; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64ZBA-NEXT: ld a0, 0(a0)
; RV64ZBA-NEXT: ret
@@ -1593,7 +1590,6 @@ define signext i16 @srliw_2_sh1add(ptr %0, i32 signext %1) {
; RV64ZBA-LABEL: srliw_2_sh1add:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: srliw a1, a1, 2
-; RV64ZBA-NEXT: zext.w a1, a1
; RV64ZBA-NEXT: sh1add a0, a1, a0
; RV64ZBA-NEXT: lh a0, 0(a0)
; RV64ZBA-NEXT: ret
@@ -1618,7 +1614,6 @@ define signext i32 @srliw_3_sh2add(ptr %0, i32 signext %1) {
; RV64ZBA-LABEL: srliw_3_sh2add:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: srliw a1, a1, 3
-; RV64ZBA-NEXT: zext.w a1, a1
; RV64ZBA-NEXT: sh2add a0, a1, a0
; RV64ZBA-NEXT: lw a0, 0(a0)
; RV64ZBA-NEXT: ret
@@ -1642,7 +1637,6 @@ define i64 @srliw_4_sh3add(ptr %0, i32 signext %1) {
; RV64ZBA-LABEL: srliw_4_sh3add:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: srliw a1, a1, 4
-; RV64ZBA-NEXT: zext.w a1, a1
; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64ZBA-NEXT: ld a0, 0(a0)
; RV64ZBA-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
index 11b64ed8a80e797..1170a3011b9ba8d 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
@@ -380,8 +380,6 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: srliw a0, a0, 27
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0)
; RV64I-NEXT: add a0, a1, a0
@@ -412,8 +410,6 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: srliw a0, a0, 27
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: lui a1, %hi(.LCPI7_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_0)
; RV64I-NEXT: add a0, a1, a0
@@ -443,8 +439,6 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: srliw a0, a0, 27
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: lui a1, %hi(.LCPI8_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI8_0)
; RV64I-NEXT: add a0, a1, a0
@@ -483,8 +477,6 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: srliw a0, a0, 27
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: lui a1, %hi(.LCPI9_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0)
; RV64I-NEXT: add a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll
index 85c4fd3a979772d..806f2e0838e294e 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll
@@ -209,17 +209,13 @@ define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind {
; RV64I-LABEL: packh_i16:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a1, 8
+; RV64I-NEXT: slliw a1, a1, 8
; RV64I-NEXT: or a0, a1, a0
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
; RV64ZBKB-LABEL: packh_i16:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: packh a0, a0, a1
-; RV64ZBKB-NEXT: slli a0, a0, 32
-; RV64ZBKB-NEXT: srli a0, a0, 32
; RV64ZBKB-NEXT: ret
%zext = zext i8 %a to i16
%zext1 = zext i8 %b to i16
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