[llvm] AMDGPU/SILowerI1Copies process phi incomings in specific order (PR #72124)

[Nicolai Hähnle via llvm-commits]

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@@ -581,10 +587,24 @@ bool SILowerI1Copies::lowerPhis() {
         assert(IncomingDef->isPHI() || PhiRegisters.count(IncomingReg));
       }
 
-      IncomingBlocks.push_back(IncomingMBB);
-      IncomingRegs.push_back(IncomingReg);
+      Incomings.push_back({IncomingReg, IncomingMBB, Register{}});
     }
 
+    // When building merge-LaneMasks, if block A dominates block B, block A
+    // must be processed first. If there is no dominate relation order does
+    // not matter since there will be no lane mask merging.
+    // To ensure this we need to sort incomings by some criteria
+    // dominates() can't be used since it is not strict weak ordering so we use
+    // DFSNumIn, DFS visitation order for nodes in the dominator tree, from
+    // MachineDominatorTree.
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nhaehnle wrote:

This comment (and the commit message) aren't *exactly* on point.

It would be perfectly possible to build merged lane masks in an arbitrary order, since the necessary virtual registers are setup in a pre-pass.

However, we'd like to do some minimal amount of constant-folding on the fly, and we can only do *that* if the defining instruction for `PrevReg` is known. And *that* is what requires the ordering here. So:
```suggestion
    // Sort the incomings such that incoming values that dominate other
    // incoming values are sorted before them. This allows us to do some
    // amount of on-the-fly constant folding.
```

https://github.com/llvm/llvm-project/pull/72124