[llvm] [RISCV][GISel] Add really basic support for FP regbank selection for G_LOAD/G_STORE. (PR #70896)

[Michael Maitland via llvm-commits]

================
@@ -158,11 +208,51 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_ANYEXT:
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ZEXT:
-  case TargetOpcode::G_LOAD:
   case TargetOpcode::G_SEXTLOAD:
   case TargetOpcode::G_ZEXTLOAD:
-  case TargetOpcode::G_STORE:
     break;
+  case TargetOpcode::G_LOAD: {
+    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
----------------
michaelmaitland wrote:

LLT is not valid if the G_LOAD/G_STORE is on a physical register. I thought it might be well-formed to write:

```
---
name:            foo
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x10
    %0:_(s32) = G_LOAD $x10(p0) :: (load (s32))
    G_STORE %0(s32), %x10(p0) :: (store (s32))
    PseudoRET
...
```

but this seems to fail sooner:
```
static unsigned int llvm::Register::virtReg2Index(llvm::Register): Assertion `Reg.isVirtual() && "Not a virtual register"' failed.
```

Looks like we don't need an isValid check.

https://github.com/llvm/llvm-project/pull/70896