[llvm] [RISCV][GlobalISel] Legalize G_ADD, G_SUB, G_AND, G_OR, G_XOR on RISC-V Vector Extension (PR #71400)

[Craig Topper via llvm-commits]

================
@@ -33,10 +33,46 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
   const LLT s32 = LLT::scalar(32);
   const LLT s64 = LLT::scalar(64);
 
+  const LLT nxv1s8 = LLT::scalable_vector(1, s8);
----------------
topperc wrote:

nxv1s8, nxv1s16, nxv1s32 require `Subtarget.getELen() == 64`. Or as it's written in SelectionDAG.

```
      // Disable the smallest fractional LMUL types if ELEN is less than         
      // RVVBitsPerBlock.   
      unsigned MinElts = RISCV::RVVBitsPerBlock / Subtarget.getELen();           
      if (VT.getVectorMinNumElements() < MinElts)                                
        return;   
```

https://github.com/llvm/llvm-project/pull/71400