[llvm] [RISCV][GISel] Add support for G_IS_FPCLASS in F and D extensions (PR #72000)

[Craig Topper via llvm-commits]

================
@@ -948,6 +952,30 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI,
   return true;
 }
 
+bool RISCVInstructionSelector::selectIsFPClass(MachineInstr &MI,
+                                               MachineIRBuilder &MIB,
+                                               MachineRegisterInfo &MRI) const {
+  Register CheckResult = MI.getOperand(0).getReg();
+  Register Src = MI.getOperand(1).getReg();
+  int64_t MaskImm = MI.getOperand(2).getImm();
+  unsigned NewOpc = MRI.getType(Src).getSizeInBits() == 32 ? RISCV::FCLASS_S
+                                                           : RISCV::FCLASS_D;
+
+  Register FClassResult = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+  // Insert FCLASS_S/D.
+  auto FClass = MIB.buildInstr(NewOpc, {FClassResult}, {Src});
+  if (!FClass.constrainAllUses(TII, TRI, RBI))
+    return false;
+  // Insert AND to check Src aginst the mask.
+  auto And = MIB.buildInstr(RISCV::ANDI, {CheckResult}, {FClassResult})
+                 .addImm(MaskImm);
+  if (!And.constrainAllUses(TII, TRI, RBI))
+    return false;
+
----------------
topperc wrote:

This test case miscompiles

```
define zeroext i1 @foo(float %x) {                                               
  %a = call i1 @llvm.is.fpclass.f32(float %x, i32 1)                             
  ret i1 %a                                                                      
}                                                                                
                                                                                 
declare i1 @llvm.is.fpclass.f32(float, i32)  
```

The resulting code is
```
        fclass.s        a0, fa0
        andi    a0, a0, 256
        andi    a0, a0, 1
        ret
```

The second andi clears the bit from the first andi.

https://github.com/llvm/llvm-project/pull/72000