[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Luke Lau via llvm-commits]

================
@@ -727,20 +812,32 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
   const RISCVSubtarget *ST;
   const TargetInstrInfo *TII;
   MachineRegisterInfo *MRI;
+  LiveIntervals *LIS = nullptr;
 
   std::vector<BlockData> BlockInfo;
   std::queue<const MachineBasicBlock *> WorkList;
+  bool IsPostRVVRegAlloc = false;
 
 public:
   static char ID;
 
-  RISCVInsertVSETVLI() : MachineFunctionPass(ID) {
+  RISCVInsertVSETVLI(bool IsPostRVVRegAlloc = false)
----------------
lukel97 wrote:

I was trying to rewrite some of the `vsetvli-insert.mir` tests over to post-ra, but I noticed there wasn't really a way to specify to llc on the command line to operate on the post-ra form. I think we might be able to get rid of the `IsPostRVVRegAlloc` boolean if we just check if LiveIntervals is available instead, something like this:

```diff
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 4663e8ea097d..70c58e7db330 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -810,13 +810,12 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
 
   std::vector<BlockData> BlockInfo;
   std::queue<const MachineBasicBlock *> WorkList;
-  bool IsSplitRA = false;
 
 public:
   static char ID;
 
   RISCVInsertVSETVLI(bool IsSplitRA = false)
-      : MachineFunctionPass(ID), IsSplitRA(IsSplitRA) {
+      : MachineFunctionPass(ID) {
     initializeRISCVInsertVSETVLIPass(*PassRegistry::getPassRegistry());
   }
   bool runOnMachineFunction(MachineFunction &MF) override;
@@ -824,13 +823,12 @@ public:
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
 
-    if (IsSplitRA) {
-      AU.addRequired<LiveIntervals>();
-      AU.addPreserved<LiveIntervals>();
-      AU.addRequired<SlotIndexes>();
-      AU.addPreserved<SlotIndexes>();
-      AU.addPreserved<LiveDebugVariables>();
-    }
+    AU.addUsedIfAvailable<LiveIntervals>();
+    AU.addPreserved<LiveIntervals>();
+    AU.addUsedIfAvailable<SlotIndexes>();
+    AU.addPreserved<SlotIndexes>();
+    AU.addUsedIfAvailable<LiveDebugVariables>();
+    AU.addPreserved<LiveDebugVariables>();
 
     MachineFunctionPass::getAnalysisUsage(AU);
   }
@@ -1072,7 +1070,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
       BuildMI(MBB, InsertPt, DL, TII->get(Opcode))
           .addReg(DestReg, RegState::Define | RegState::Dead)
           .addReg(AVLReg,
-                  (IsSplitRA && MRI->def_empty(AVLReg)) ? RegState::Undef : 0)
+                  (LIS && MRI->def_empty(AVLReg)) ? RegState::Undef : 0)
           .addImm(Info.encodeVTYPE());
   fixupModifyVRegLIFromVSETVL(NeedFixupMI, LIS);
 }
@@ -1652,7 +1650,7 @@ void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) {
       NeedFixup.push_back(Reg);
     }
     MI->eraseFromParent();
-    if (IsSplitRA)
+    if (LIS)
       LIS->RemoveMachineInstrFromMaps(*MI);
   }
 
@@ -1691,10 +1689,7 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
   TII = ST->getInstrInfo();
   MRI = &MF.getRegInfo();
 
-  if (IsSplitRA)
-    LIS = &getAnalysis<LiveIntervals>();
-  else
-    LIS = nullptr;
+  LIS = getAnalysisIfAvailable<LiveIntervals>();
 
   assert(BlockInfo.empty() && "Expect empty block infos");
   BlockInfo.resize(MF.getNumBlockIDs());

```

https://github.com/llvm/llvm-project/pull/70549