[llvm] [DAG] narrowExtractedVectorBinOp - ensure we limit late node creation to LegalOperations only (PR #72130)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 9aefa5cb679a6f42a0d343c93a25a66b0374b3c6 a5e25b1d1a68de9c404a198f0bee5b251247b1fb -- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/lib/Target/X86/X86ISelLowering.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 99f225a7d7..49d02bdb68 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -41379,10 +41379,10 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
     case X86ISD::VSRLV:
     case X86ISD::VSRAV:
       // Float Ops.
-    case X86ISD::FMAX: 
-    case X86ISD::FMIN: 
-    case X86ISD::FMAXC: 
-    case X86ISD::FMINC: 
+    case X86ISD::FMAX:
+    case X86ISD::FMIN:
+    case X86ISD::FMAXC:
+    case X86ISD::FMINC:
       // Horizontal Ops.
     case X86ISD::HADD:
     case X86ISD::HSUB:

``````````

</details>


https://github.com/llvm/llvm-project/pull/72130