[llvm] [RISCV][GISel] Add really basic support for FP regbank selection for G_LOAD/G_STORE. (PR #70896)

[Michael Maitland via llvm-commits]

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@@ -158,11 +208,51 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_ANYEXT:
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ZEXT:
-  case TargetOpcode::G_LOAD:
   case TargetOpcode::G_SEXTLOAD:
   case TargetOpcode::G_ZEXTLOAD:
-  case TargetOpcode::G_STORE:
     break;
+  case TargetOpcode::G_LOAD: {
+    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+    // Use FPR64 for s64 loads on rv32.
+    if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
+      OperandsMapping =
+          getOperandsMapping({getFPValueMapping(64), GPRValueMapping});
+      break;
+    }
+
+    // Check if that load feeds fp instructions.
+    // In that case, we want the default mapping to be on FPR
+    // instead of blind map every scalar to GPR.
+    if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
+               [&](const MachineInstr &UseMI) {
+                 // If we have at least one direct use in a FP instruction,
+                 // assume this was a floating point load in the IR. If it was
+                 // not, we would have had a bitcast before reaching that
+                 // instruction.
+                 return onlyUsesFP(UseMI);
+               })) {
+      OperandsMapping = getOperandsMapping(
+          {getFPValueMapping(Ty.getSizeInBits()), GPRValueMapping});
+    }
+
+    break;
+  }
+  case TargetOpcode::G_STORE: {
+    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+    // Use FPR64 for s64 stores on rv32.
+    if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
+      OperandsMapping =
+          getOperandsMapping({getFPValueMapping(64), GPRValueMapping});
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michaelmaitland wrote:

On rv32, are you guaranteed to have FPR64?

https://github.com/llvm/llvm-project/pull/70896