[llvm] [RISCV] Use correct register class for Z[df]inx inline asm (PR #71872)
Nemanja Ivanovic via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 13 06:45:06 PST 2023
https://github.com/nemanjai updated https://github.com/llvm/llvm-project/pull/71872
>From 283c0180c6595ef7c14d7123f772fe7ae7157044 Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
Date: Thu, 9 Nov 2023 22:48:43 +0100
Subject: [PATCH 1/2] [RISCV] Use correct register class for Z[df]inx inline
asm
Allocate a register of the correct register class for inline
asm constraint "r" when used for FP values with -Zfinx/-Zdinx.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 ++
.../CodeGen/RISCV/zdinx-asm-constraint.ll | 43 +++++++++++++++++++
2 files changed, 47 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8d13563eb138150..1429c9375f1a29b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18370,6 +18370,10 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
// TODO: Support fixed vectors up to XLen for P extension?
if (VT.isVector())
break;
+ if (VT == MVT::f32 && Subtarget.hasStdExtZfinx())
+ return std::make_pair(0U, &RISCV::GPRF32RegClass);
+ if (VT == MVT::f64 && Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit())
+ return std::make_pair(0U, &RISCV::GPRPF64RegClass);
return std::make_pair(0U, &RISCV::GPRNoX0RegClass);
case 'f':
if (Subtarget.hasStdExtZfhOrZfhmin() && VT == MVT::f16)
diff --git a/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll b/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
new file mode 100644
index 000000000000000..ef5c08f80b03426
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
+; RUN: -target-abi=ilp32 | FileCheck %s
+define dso_local void @zdinx_asm(ptr nocapture noundef writeonly %a, double noundef %b, double noundef %c) nounwind {
+; CHECK-LABEL: zdinx_asm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: sw a1, 8(sp)
+; CHECK-NEXT: sw a2, 12(sp)
+; CHECK-NEXT: lw a6, 8(sp)
+; CHECK-NEXT: lw a7, 12(sp)
+; CHECK-NEXT: sw a3, 8(sp)
+; CHECK-NEXT: sw a4, 12(sp)
+; CHECK-NEXT: lw a2, 8(sp)
+; CHECK-NEXT: lw a3, 12(sp)
+; CHECK-NEXT: #APP
+; CHECK-NEXT: fsgnjx.d a2, a6, a2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: sw a2, 8(a0)
+; CHECK-NEXT: sw a3, 12(a0)
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+entry:
+ %arrayidx = getelementptr inbounds double, ptr %a, i32 1
+ %0 = tail call double asm "fsgnjx.d $0, $1, $2", "=r,r,r"(double %b, double %c)
+ store double %0, ptr %arrayidx, align 8
+ ret void
+}
+
+define dso_local void @zfinx_asm(ptr nocapture noundef writeonly %a, float noundef %b, float noundef %c) nounwind {
+; CHECK-LABEL: zfinx_asm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: fsgnjx.s a1, a1, a2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: sw a1, 4(a0)
+; CHECK-NEXT: ret
+entry:
+ %arrayidx = getelementptr inbounds float, ptr %a, i32 1
+ %0 = tail call float asm "fsgnjx.s $0, $1, $2", "=r,r,r"(float %b, float %c)
+ store float %0, ptr %arrayidx, align 8
+ ret void
+}
>From 79768ec90fcb088cb5b861331ffcbca4349ea40c Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic <nemanja at synopsys.com>
Date: Mon, 13 Nov 2023 15:44:26 +0100
Subject: [PATCH 2/2] Also use the correct register class for half precision
with zhinx.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 ++
llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll | 17 ++++++++++++++++-
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1429c9375f1a29b..0fe8ff0c17b3bb5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18370,6 +18370,8 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
// TODO: Support fixed vectors up to XLen for P extension?
if (VT.isVector())
break;
+ if (VT == MVT::f16 && Subtarget.hasStdExtZhinxOrZhinxmin())
+ return std::make_pair(0U, &RISCV::GPRF16RegClass);
if (VT == MVT::f32 && Subtarget.hasStdExtZfinx())
return std::make_pair(0U, &RISCV::GPRF32RegClass);
if (VT == MVT::f64 && Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit())
diff --git a/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll b/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
index ef5c08f80b03426..63c46ca4eafce82 100644
--- a/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
+++ b/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32 | FileCheck %s
+; RUN: -target-abi=ilp32 -mattr=+zhinx | FileCheck %s
define dso_local void @zdinx_asm(ptr nocapture noundef writeonly %a, double noundef %b, double noundef %c) nounwind {
; CHECK-LABEL: zdinx_asm:
; CHECK: # %bb.0: # %entry
@@ -41,3 +41,18 @@ entry:
store float %0, ptr %arrayidx, align 8
ret void
}
+
+define dso_local void @zhinx_asm(ptr nocapture noundef writeonly %a, half noundef %b, half noundef %c) nounwind {
+; CHECK-LABEL: zhinx_asm:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: fsgnjx.h a1, a1, a2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: sh a1, 2(a0)
+; CHECK-NEXT: ret
+entry:
+ %arrayidx = getelementptr inbounds half, ptr %a, i32 1
+ %0 = tail call half asm "fsgnjx.h $0, $1, $2", "=r,r,r"(half %b, half %c)
+ store half %0, ptr %arrayidx, align 8
+ ret void
+}
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