[llvm] [RISCV] Split regalloc between RVV and other (PR #72096)
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Mon Nov 13 02:06:57 PST 2023
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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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git-clang-format --diff 4cc791bc98e075879f8c379f17e0b0369d57a40d 5b2ac611f2bb7c4744ca5df31c938666b3e4161e -- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 15f1948551..524c1a5ca5 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -90,9 +90,10 @@ static cl::opt<bool>
cl::desc("Enable the loop data prefetch pass"),
cl::init(true));
-static cl::opt<bool> EnableSplitRegAlloc("riscv-split-regalloc", cl::Hidden,
- cl::desc("Enable Split RegisterAlloc for RVV"),
- cl::init(false));
+static cl::opt<bool>
+ EnableSplitRegAlloc("riscv-split-regalloc", cl::Hidden,
+ cl::desc("Enable Split RegisterAlloc for RVV"),
+ cl::init(false));
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
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https://github.com/llvm/llvm-project/pull/72096
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