[llvm] [RISCV] RISC-V split register allocation and move vsetvl pass in between (PR #70549)

[Luke Lau via llvm-commits]

lukel97 wrote:

I tried out this patch and I agree that the register allocation split should be done in a separate PR, with the split just enabled by default: There were only four lit test diffs, none of them were regressions. I also ran this on the llvm-test-suite for rv64gv and couldn't find any regressions, just some shuffling about of registers, here's the diff: 
[regalloc-split.patch](https://github.com/llvm/llvm-project/files/13332331/regalloc-split.patch)


https://github.com/llvm/llvm-project/pull/70549