[llvm] [RISCV][CodeGenPrepare] Remove duplicated transform for zext. NFC. (PR #72053)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 12 05:56:23 PST 2023
https://github.com/dtcxzyw created https://github.com/llvm/llvm-project/pull/72053
After #71534 and #72052, the transform `zext -> zext nneg` in `RISCVCodeGenPrepare` is redundant.
>From 0a9801c2343d6feb17e3f2afdad389452b8c966f Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Sun, 12 Nov 2023 21:55:32 +0800
Subject: [PATCH] [RISCV][CodeGenPrepare] Remove duplicated transform for zext.
NFC.
---
llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp | 40 --------------
llvm/test/CodeGen/RISCV/iabs.ll | 2 +-
.../CodeGen/RISCV/riscv-codegenprepare-asm.ll | 4 +-
.../CodeGen/RISCV/riscv-codegenprepare.ll | 53 +------------------
4 files changed, 4 insertions(+), 95 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
index 7bc7e3924ca7026..f9d8401bab7b396 100644
--- a/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
@@ -28,8 +28,6 @@ using namespace llvm;
#define DEBUG_TYPE "riscv-codegenprepare"
#define PASS_NAME "RISC-V CodeGenPrepare"
-STATISTIC(NumZExtToSExt, "Number of SExt instructions converted to ZExt");
-
namespace {
class RISCVCodeGenPrepare : public FunctionPass,
@@ -52,49 +50,11 @@ class RISCVCodeGenPrepare : public FunctionPass,
}
bool visitInstruction(Instruction &I) { return false; }
- bool visitZExtInst(ZExtInst &I);
bool visitAnd(BinaryOperator &BO);
};
} // end anonymous namespace
-bool RISCVCodeGenPrepare::visitZExtInst(ZExtInst &ZExt) {
- if (!ST->is64Bit())
- return false;
-
- if (ZExt.hasNonNeg())
- return false;
-
- Value *Src = ZExt.getOperand(0);
-
- // We only care about ZExt from i32 to i64.
- if (!ZExt.getType()->isIntegerTy(64) || !Src->getType()->isIntegerTy(32))
- return false;
-
- // Look for an opportunity to infer nneg on a zext if we can determine that
- // the sign bit of X is zero via a dominating condition. This often occurs
- // with widened induction variables.
- if (isImpliedByDomCondition(ICmpInst::ICMP_SGE, Src,
- Constant::getNullValue(Src->getType()), &ZExt,
- *DL).value_or(false)) {
- ZExt.setNonNeg(true);
- ++NumZExtToSExt;
- return true;
- }
-
- // Convert (zext (abs(i32 X, i1 1))) -> (zext nneg (abs(i32 X, i1 1))). If abs of
- // INT_MIN is poison, the sign bit is zero.
- // TODO: Move this to instcombine now that we have zext nneg in IR.
- using namespace PatternMatch;
- if (match(Src, m_Intrinsic<Intrinsic::abs>(m_Value(), m_One()))) {
- ZExt.setNonNeg(true);
- ++NumZExtToSExt;
- return true;
- }
-
- return false;
-}
-
// Try to optimize (i64 (and (zext/sext (i32 X), C1))) if C1 has bit 31 set,
// but bits 63:32 are zero. If we know that bit 31 of X is 0, we can fill
// the upper 32 bits with ones.
diff --git a/llvm/test/CodeGen/RISCV/iabs.ll b/llvm/test/CodeGen/RISCV/iabs.ll
index 036a5d49d441c2d..cb64e24128b5e37 100644
--- a/llvm/test/CodeGen/RISCV/iabs.ll
+++ b/llvm/test/CodeGen/RISCV/iabs.ll
@@ -494,7 +494,7 @@ define i64 @zext_abs32(i32 %x) {
; RV64ZBB-NEXT: max a0, a0, a1
; RV64ZBB-NEXT: ret
%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
- %zext = zext i32 %abs to i64
+ %zext = zext nneg i32 %abs to i64
ret i64 %zext
}
diff --git a/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll b/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
index c343ef5b451de8d..7cbe5e73d5241a4 100644
--- a/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
+++ b/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
@@ -24,7 +24,7 @@ entry:
br i1 %cmp3, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
- %wide.trip.count = zext i32 %n to i64
+ %wide.trip.count = zext nneg i32 %n to i64
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
@@ -84,7 +84,7 @@ entry:
br i1 %cmp3, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
- %wide.trip.count = zext i32 %n to i64
+ %wide.trip.count = zext nneg i32 %n to i64
%xtraiter = and i64 %wide.trip.count, 1
%0 = icmp eq i32 %n, 1
br i1 %0, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body.preheader.new
diff --git a/llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll b/llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll
index b4f0918635650b9..0e4e04af4a3fe7e 100644
--- a/llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll
+++ b/llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll
@@ -1,57 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -S -riscv-codegenprepare -mtriple=riscv64 | FileCheck %s
-; Test that we can convert the %wide.trip.count zext to a sext. The dominating
-; condition %cmp3 ruled out %n being negative.
-define void @test1(ptr nocapture noundef %a, i32 noundef signext %n) {
-; CHECK-LABEL: @test1(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[N:%.*]], 0
-; CHECK-NEXT: br i1 [[CMP3]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]
-; CHECK: for.body.preheader:
-; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i64
-; CHECK-NEXT: br label [[FOR_BODY:%.*]]
-; CHECK: for.cond.cleanup.loopexit:
-; CHECK-NEXT: br label [[FOR_COND_CLEANUP]]
-; CHECK: for.cond.cleanup:
-; CHECK-NEXT: ret void
-; CHECK: for.body:
-; CHECK-NEXT: [[LSR_IV5:%.*]] = phi i64 [ [[WIDE_TRIP_COUNT]], [[FOR_BODY_PREHEADER]] ], [ [[LSR_IV_NEXT:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[LSR_IV:%.*]] = phi ptr [ [[A:%.*]], [[FOR_BODY_PREHEADER]] ], [ [[UGLYGEP:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[LSR_IV]], align 4
-; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 4
-; CHECK-NEXT: store i32 [[ADD]], ptr [[LSR_IV]], align 4
-; CHECK-NEXT: [[UGLYGEP]] = getelementptr i8, ptr [[LSR_IV]], i64 4
-; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV5]], -1
-; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0
-; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]], label [[FOR_BODY]]
-;
-entry:
- %cmp3 = icmp sgt i32 %n, 0
- br i1 %cmp3, label %for.body.preheader, label %for.cond.cleanup
-
-for.body.preheader: ; preds = %entry
- %wide.trip.count = zext i32 %n to i64
- br label %for.body
-
-for.cond.cleanup.loopexit: ; preds = %for.body
- br label %for.cond.cleanup
-
-for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
- ret void
-
-for.body: ; preds = %for.body.preheader, %for.body
- %lsr.iv5 = phi i64 [ %wide.trip.count, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
- %lsr.iv = phi ptr [ %a, %for.body.preheader ], [ %uglygep, %for.body ]
- %0 = load i32, ptr %lsr.iv, align 4
- %add = add nsw i32 %0, 4
- store i32 %add, ptr %lsr.iv, align 4
- %uglygep = getelementptr i8, ptr %lsr.iv, i64 4
- %lsr.iv.next = add nsw i64 %lsr.iv5, -1
- %exitcond.not = icmp eq i64 %lsr.iv.next, 0
- br i1 %exitcond.not, label %for.cond.cleanup.loopexit, label %for.body
-}
-
; Make sure we convert the 4294967294 in for.body.preheader.new to -2 based on
; the upper 33 bits being zero by the dominating condition %cmp3.
define void @test2(ptr nocapture noundef %a, i32 noundef signext %n) {
@@ -101,7 +50,7 @@ entry:
br i1 %cmp3, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
- %wide.trip.count = zext i32 %n to i64
+ %wide.trip.count = zext nneg i32 %n to i64
%xtraiter = and i64 %wide.trip.count, 1
%0 = icmp eq i32 %n, 1
br i1 %0, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body.preheader.new
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