[llvm] [llvm] Adding scalarization of `llvm.vector.insert` (PR #71614)

[David Green via llvm-commits]

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@@ -5891,8 +5910,11 @@ SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
     InOp1 = GetWidenedVector(InOp1);
     InOp2 = GetWidenedVector(InOp2);
   } else {
-    InOp1 = DAG.WidenVector(InOp1, SDLoc(N));
-    InOp2 = DAG.WidenVector(InOp2, SDLoc(N));
+    do {
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davemgreen wrote:

Thats always the question, and Im not sure there is a way to specify the types for operations separately. Looking through the example though, it appears that the `v1i16 setcc v1f16` is being created in the AArch64 backend inside performVSelectCombine.

I've put up # as a possible fix. It just tries to prevent the generation of `v1i16 setcc v1f16`, which so long as they dont get generated from anywhere else seems to work OK, even if the code generated it not necessarily optimal. Let me know what you think.

https://github.com/llvm/llvm-project/pull/71614