[llvm] 3e60693 - [RISCV][GISel] Rename PartialMappingIdx and ValueMappingsIdx to use register bank name with B suffix. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-12T00:09:01-08:00
New Revision: 3e60693422cc10de5b593d6bd532a82ceb9fac9c

URL: https://github.com/llvm/llvm-project/commit/3e60693422cc10de5b593d6bd532a82ceb9fac9c
DIFF: https://github.com/llvm/llvm-project/commit/3e60693422cc10de5b593d6bd532a82ceb9fac9c.diff

LOG: [RISCV][GISel] Rename PartialMappingIdx and ValueMappingsIdx to use register bank name with B suffix. NFC

PartialMappingIdx refers to an entry in the PartMappings table that
includes a RegBank and a size. So I think the PartialMappingIdx should
be named using the name of the register bank concatenated with the size.

So the indices are now PMI_GPRB32, PMI_GPRB64, PMI_FPRB32, PMI_FPRB64.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index e10ed0af659ed4a..a9908abf642372c 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -32,39 +32,39 @@ const RegisterBankInfo::PartialMapping PartMappings[] = {
 };
 
 enum PartialMappingIdx {
-  PMI_GPR32 = 0,
-  PMI_GPR64 = 1,
-  PMI_FPR32 = 2,
-  PMI_FPR64 = 3,
+  PMI_GPRB32 = 0,
+  PMI_GPRB64 = 1,
+  PMI_FPRB32 = 2,
+  PMI_FPRB64 = 3,
 };
 
 const RegisterBankInfo::ValueMapping ValueMappings[] = {
     // Invalid value mapping.
     {nullptr, 0},
     // Maximum 3 GPR operands; 32 bit.
-    {&PartMappings[PMI_GPR32], 1},
-    {&PartMappings[PMI_GPR32], 1},
-    {&PartMappings[PMI_GPR32], 1},
+    {&PartMappings[PMI_GPRB32], 1},
+    {&PartMappings[PMI_GPRB32], 1},
+    {&PartMappings[PMI_GPRB32], 1},
     // Maximum 3 GPR operands; 64 bit.
-    {&PartMappings[PMI_GPR64], 1},
-    {&PartMappings[PMI_GPR64], 1},
-    {&PartMappings[PMI_GPR64], 1},
+    {&PartMappings[PMI_GPRB64], 1},
+    {&PartMappings[PMI_GPRB64], 1},
+    {&PartMappings[PMI_GPRB64], 1},
     // Maximum 3 FPR operands; 32 bit.
-    {&PartMappings[PMI_FPR32], 1},
-    {&PartMappings[PMI_FPR32], 1},
-    {&PartMappings[PMI_FPR32], 1},
+    {&PartMappings[PMI_FPRB32], 1},
+    {&PartMappings[PMI_FPRB32], 1},
+    {&PartMappings[PMI_FPRB32], 1},
     // Maximum 3 FPR operands; 64 bit.
-    {&PartMappings[PMI_FPR64], 1},
-    {&PartMappings[PMI_FPR64], 1},
-    {&PartMappings[PMI_FPR64], 1},
+    {&PartMappings[PMI_FPRB64], 1},
+    {&PartMappings[PMI_FPRB64], 1},
+    {&PartMappings[PMI_FPRB64], 1},
 };
 
 enum ValueMappingsIdx {
   InvalidIdx = 0,
-  GPR32Idx = 1,
-  GPR64Idx = 4,
-  FPR32Idx = 7,
-  FPR64Idx = 10,
+  GPRB32Idx = 1,
+  GPRB64Idx = 4,
+  FPRB32Idx = 7,
+  FPRB64Idx = 10,
 };
 } // namespace RISCV
 } // namespace llvm
@@ -105,7 +105,7 @@ RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
 
 static const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
   assert(Size == 32 || Size == 64);
-  unsigned Idx = Size == 64 ? RISCV::FPR64Idx : RISCV::FPR32Idx;
+  unsigned Idx = Size == 64 ? RISCV::FPRB64Idx : RISCV::FPRB32Idx;
   return &RISCV::ValueMappings[Idx];
 }
 
@@ -129,7 +129,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
 
   unsigned NumOperands = MI.getNumOperands();
   const ValueMapping *GPRValueMapping =
-      &RISCV::ValueMappings[GPRSize == 64 ? RISCV::GPR64Idx : RISCV::GPR32Idx];
+      &RISCV::ValueMappings[GPRSize == 64 ? RISCV::GPRB64Idx
+                                          : RISCV::GPRB32Idx];
   const ValueMapping *OperandsMapping = GPRValueMapping;
 
   switch (Opc) {