[llvm] 7965a21 - [RISCV] Add more packh patterns.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-11T19:31:23-08:00
New Revision: 7965a21f7a5056d28c7746b8282c28fa6095309a

URL: https://github.com/llvm/llvm-project/commit/7965a21f7a5056d28c7746b8282c28fa6095309a
DIFF: https://github.com/llvm/llvm-project/commit/7965a21f7a5056d28c7746b8282c28fa6095309a.diff

LOG: [RISCV] Add more packh patterns.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    llvm/test/CodeGen/RISCV/rv32zbkb.ll
    llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll
    llvm/test/CodeGen/RISCV/rv64zbkb.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 034d67f0f928f5f..84e2bdd4fbbbd72 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1864,6 +1864,12 @@ def : Pat<(i64 (shl (and GPR:$rs1, 0xffffffff), uimm5:$shamt)),
           (SRLI (SLLI GPR:$rs1, 32), (ImmSubFrom32 uimm5:$shamt))>;
 }
 
+class binop_allhusers<SDPatternOperator operator>
+    : PatFrag<(ops node:$lhs, node:$rhs),
+              (XLenVT (operator node:$lhs, node:$rhs)), [{
+  return hasAllHUsers(Node);
+}]>;
+
 // PatFrag to allow ADDW/SUBW/MULW/SLLW to be selected from i64 add/sub/mul/shl
 // if only the lower 32 bits of their result is used.
 class binop_allwusers<SDPatternOperator operator>

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 1ecbbd6323b0a44..d1c29842b85d38a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -643,6 +643,10 @@ def : Pat<(or (shl (zexti8 (XLenVT GPR:$rs2)), (XLenVT 8)),
 def : Pat<(and (or (shl GPR:$rs2, (XLenVT 8)),
                    (zexti8 (XLenVT GPR:$rs1))), 0xFFFF),
           (PACKH GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(binop_allhusers<or> (shl GPR:$rs2, (XLenVT 8)),
+                               (zexti8 (XLenVT GPR:$rs1))),
+          (PACKH GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbkb]
 
 let Predicates = [HasStdExtZbkb, IsRV32] in
@@ -853,6 +857,9 @@ def : Pat<(or (and (shl GPR:$rs2, (i64 8)), 0xFFFF),
 def : Pat<(or (shl (zexti8i32 (i32 GPR:$rs2)), (i64 8)),
               (zexti8i32 (i32 GPR:$rs1))),
           (PACKH GPR:$rs1, GPR:$rs2)>;
+def : Pat<(and (anyext (or (shl GPR:$rs2, (XLenVT 8)),
+                           (zexti8i32 (i32 GPR:$rs1)))), 0xFFFF),
+          (PACKH GPR:$rs1, GPR:$rs2)>;
 
 def : Pat<(i32 (or (shl GPR:$rs2, (i64 16)), (zexti16i32 (i32 GPR:$rs1)))),
           (PACKW GPR:$rs1, GPR:$rs2)>;

diff  --git a/llvm/test/CodeGen/RISCV/rv32zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbkb.ll
index 9a434e2e68608c9..33116d16595a446 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbkb.ll
@@ -231,3 +231,27 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
   %8 = or i16 %6, %7
   ret i16 %8
 }
+
+define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {
+; RV32I-LABEL: packh_i16_3:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    add a0, a1, a0
+; RV32I-NEXT:    slli a0, a0, 8
+; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    sh a0, 0(a3)
+; RV32I-NEXT:    ret
+;
+; RV32ZBKB-LABEL: packh_i16_3:
+; RV32ZBKB:       # %bb.0:
+; RV32ZBKB-NEXT:    add a0, a1, a0
+; RV32ZBKB-NEXT:    packh a0, a2, a0
+; RV32ZBKB-NEXT:    sh a0, 0(a3)
+; RV32ZBKB-NEXT:    ret
+  %4 = add i8 %1, %0
+  %5 = zext i8 %4 to i16
+  %6 = shl i16 %5, 8
+  %7 = zext i8 %2 to i16
+  %8 = or i16 %6, %7
+  store i16 %8, ptr %p
+  ret void
+}

diff  --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll
index 1dbee8b283d1515..85c4fd3a979772d 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll
@@ -241,10 +241,7 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
 ; RV64ZBKB-LABEL: packh_i16_2:
 ; RV64ZBKB:       # %bb.0:
 ; RV64ZBKB-NEXT:    add a0, a1, a0
-; RV64ZBKB-NEXT:    slli a0, a0, 8
-; RV64ZBKB-NEXT:    or a0, a0, a2
-; RV64ZBKB-NEXT:    slli a0, a0, 48
-; RV64ZBKB-NEXT:    srli a0, a0, 48
+; RV64ZBKB-NEXT:    packh a0, a2, a0
 ; RV64ZBKB-NEXT:    ret
   %4 = add i8 %1, %0
   %5 = zext i8 %4 to i16

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/rv64zbkb.ll
index dd6248233975a7e..db1330b0a63bd36 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbkb.ll
@@ -247,6 +247,30 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
   ret i16 %8
 }
 
+define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {
+; RV64I-LABEL: packh_i16_3:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    add a0, a1, a0
+; RV64I-NEXT:    slli a0, a0, 8
+; RV64I-NEXT:    or a0, a0, a2
+; RV64I-NEXT:    sh a0, 0(a3)
+; RV64I-NEXT:    ret
+;
+; RV64ZBKB-LABEL: packh_i16_3:
+; RV64ZBKB:       # %bb.0:
+; RV64ZBKB-NEXT:    add a0, a1, a0
+; RV64ZBKB-NEXT:    packh a0, a2, a0
+; RV64ZBKB-NEXT:    sh a0, 0(a3)
+; RV64ZBKB-NEXT:    ret
+  %4 = add i8 %1, %0
+  %5 = zext i8 %4 to i16
+  %6 = shl i16 %5, 8
+  %7 = zext i8 %2 to i16
+  %8 = or i16 %6, %7
+  store i16 %8, ptr %p
+  ret void
+}
+
 define i64 @pack_i64_allWUsers(i32 signext %0, i32 signext %1, i32 signext %2) {
 ; RV64I-LABEL: pack_i64_allWUsers:
 ; RV64I:       # %bb.0: