[llvm] 647c490 - [RISCV] Add an add.uw pattern using zext for -riscv-experimental-rv64-legal-i32 and global isel

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-10T21:36:29-08:00
New Revision: 647c490f8a994e9632f990d6bdf23d40fc0ffeb3

URL: https://github.com/llvm/llvm-project/commit/647c490f8a994e9632f990d6bdf23d40fc0ffeb3
DIFF: https://github.com/llvm/llvm-project/commit/647c490f8a994e9632f990d6bdf23d40fc0ffeb3.diff

LOG: [RISCV] Add an add.uw pattern using zext for -riscv-experimental-rv64-legal-i32 and global isel

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
    llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 9ab580de33a20ec..e7118b1339bfb1a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -848,6 +848,8 @@ def : Pat<(i32 (rotl GPR:$rs1, uimm5:$rs2)),
 
 let Predicates = [HasStdExtZba, IsRV64] in {
 def : Pat<(zext GPR:$src), (ADD_UW GPR:$src, (XLenVT X0))>;
+def : Pat<(i64 (add_non_imm12 (zext GPR:$rs1), GPR:$rs2)),
+          (ADD_UW GPR:$rs1, GPR:$rs2)>;
 }
 
 let Predicates = [HasStdExtZbs, IsRV64] in {

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
index c826bce2ad98cd9..ade3d987244e0b0 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
@@ -327,3 +327,26 @@ body:             |
     %7:gprb(s64) = G_ANYEXT %6
     $x10 = COPY %7(s64)
 ...
+---
+name:            adduw
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; CHECK-LABEL: name: adduw
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; CHECK-NEXT: [[ADD_UW:%[0-9]+]]:gpr = ADD_UW [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x10 = COPY [[ADD_UW]]
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s32) = G_TRUNC %0
+    %3:gprb(s64) = G_ZEXT %2
+    %4:gprb(s64) = G_ADD %3, %1
+    $x10 = COPY %4(s64)
+...

diff  --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
index d2ae64dc5367ed0..a58114294e836bb 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
@@ -82,6 +82,29 @@ define signext i8 @adduw_2(i32 signext %0, ptr %1) {
   ret i8 %5
 }
 
+define signext i8 @adduw_3(i32 signext %0, ptr %1) {
+; RV64I-LABEL: adduw_3:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, 1
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    add a0, a1, a0
+; RV64I-NEXT:    lb a0, 0(a0)
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: adduw_3:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    addi a0, a0, 1
+; RV64ZBA-NEXT:    add.uw a0, a0, a1
+; RV64ZBA-NEXT:    lb a0, 0(a0)
+; RV64ZBA-NEXT:    ret
+  %add = add i32 %0, 1
+  %3 = zext i32 %add to i64
+  %4 = getelementptr inbounds i8, ptr %1, i64 %3
+  %5 = load i8, ptr %4
+  ret i8 %5
+}
+
 define i64 @zextw_i64(i64 %a) nounwind {
 ; RV64I-LABEL: zextw_i64:
 ; RV64I:       # %bb.0: