[llvm] [X86][MC] Support encoding of EGPR for APX (PR #71909)

[Shengchen Kan via llvm-commits]

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@@ -1086,19 +1162,25 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
   case X86II::MRMSrcReg4VOp3: {
     // Instruction format for 4VOp3:
     //   src1(ModR/M), src2(ModR/M), src3(VEX_4V)
+    if ((TSFlags & X86II::EncodingMask) == X86II::EVEX) {
+      Prefix.setRR2(MI, CurOp++);
+      Prefix.setBB2(MI, CurOp++);
+      Prefix.set4V(MI, CurOp++);
+      break;
+    }
     Prefix.setR(MI, CurOp++);
     Prefix.setB(MI, CurOp++);
     Prefix.set4V(MI, CurOp++);
     break;
   }
   case X86II::MRMSrcRegOp4: {
     //  dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
-    Prefix.setR(MI, CurOp++);
+    Prefix.setRR2(MI, CurOp++);
     Prefix.set4V(MI, CurOp++);
     // Skip second register source (encoded in Imm[7:4])
     ++CurOp;
 
-    Prefix.setB(MI, CurOp);
+    Prefix.setBB2(MI, CurOp);
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KanRobert wrote:

Good suggestion. It's related to how do we extend registers in EVEX prefix. This description has been missing since we introduced AVX512. Let me add it.

https://github.com/llvm/llvm-project/pull/71909