[llvm] [RISCV] Use correct register class for Z[df]inx inline asm (PR #71872)

[Craig Topper via llvm-commits]

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@@ -18370,6 +18370,10 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
       // TODO: Support fixed vectors up to XLen for P extension?
       if (VT.isVector())
         break;
+      if (VT == MVT::f32 && Subtarget.hasStdExtZfinx())
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topperc wrote:

Is Zhinx broken too?

https://github.com/llvm/llvm-project/pull/71872