[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)

[Craig Topper via llvm-commits]

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@@ -14,3 +14,7 @@ def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
 
 /// Floating Point Registers: F.
 def FPRRegBank : RegisterBank<"FPRB", [FPR64]>;
+
+/// Vector Regististers: V.
+def VRRegBank : RegisterBank<"VRB", [VR]>;
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topperc wrote:

Is [VR] enough to make tablegen consider all of the register classes as being part of the bank? You can check the`VRRegBankCoverageData` in lib/Target/RISCV/RISCVGenRegisterBank.inc in your build directory

https://github.com/llvm/llvm-project/pull/71541